1/*******************************************************************************
2* Copyright 2020-2022 Intel Corporation
3*
4* Licensed under the Apache License, Version 2.0 (the "License");
5* you may not use this file except in compliance with the License.
6* You may obtain a copy of the License at
7*
8* http://www.apache.org/licenses/LICENSE-2.0
9*
10* Unless required by applicable law or agreed to in writing, software
11* distributed under the License is distributed on an "AS IS" BASIS,
12* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13* See the License for the specific language governing permissions and
14* limitations under the License.
15*******************************************************************************/
16
17#ifndef CPU_X64_PRELU_JIT_PRELU_UTILS_HPP
18#define CPU_X64_PRELU_JIT_PRELU_UTILS_HPP
19
20#include <set>
21
22#include "cpu/x64/cpu_isa_traits.hpp"
23#include "cpu/x64/jit_generator.hpp"
24
25namespace dnnl {
26namespace impl {
27
28struct memory_desc_wrapper;
29
30namespace cpu {
31namespace x64 {
32namespace prelu {
33
34enum class bcast {
35 full,
36 per_oc_blocked,
37 per_oc_n_spatial_c,
38 per_oc_n_c_spatial,
39 unsupported
40};
41
42bcast get_bcast_type(
43 const memory_desc_wrapper &lhs, const memory_desc_wrapper &rhs);
44cpu_isa_t get_supported_isa();
45int get_n_vregs(const cpu_isa_t &isa) noexcept;
46bool dt_supported(const std::set<data_type_t> &tensor_data_types) noexcept;
47bool is_s8u8(const std::set<data_type_t> &tensor_data_types) noexcept;
48int get_simd_w(const std::set<data_type_t> &tensor_data_types) noexcept;
49size_t c_blk_nelems(const memory_desc_t *mem, bool padding) noexcept;
50size_t get_block_tail_size(const memory_desc_t *mem) noexcept;
51void apply_zero_padding(jit_generator *host, const size_t tail_size,
52 const data_type_t dt, const size_t block_tail_size,
53 const Xbyak::Reg64 &reg_dst, const Xbyak::Reg64 *reg_offset) noexcept;
54
55} // namespace prelu
56} // namespace x64
57} // namespace cpu
58} // namespace impl
59} // namespace dnnl
60
61#endif
62