1 | /******************************************************************************* |
2 | * Copyright 2020-2022 Intel Corporation |
3 | * Copyright 2022 FUJITSU LIMITED |
4 | * |
5 | * Licensed under the Apache License, Version 2.0 (the "License"); |
6 | * you may not use this file except in compliance with the License. |
7 | * You may obtain a copy of the License at |
8 | * |
9 | * http://www.apache.org/licenses/LICENSE-2.0 |
10 | * |
11 | * Unless required by applicable law or agreed to in writing, software |
12 | * distributed under the License is distributed on an "AS IS" BASIS, |
13 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
14 | * See the License for the specific language governing permissions and |
15 | * limitations under the License. |
16 | *******************************************************************************/ |
17 | |
18 | #include "common/impl_list_item.hpp" |
19 | #include "cpu/reorder/cpu_reorder.hpp" |
20 | |
21 | namespace dnnl { |
22 | namespace impl { |
23 | namespace cpu { |
24 | |
25 | // clang-format off |
26 | |
27 | const impl_list_map_t ®ular_s8_impl_list_map() { |
28 | static const impl_list_map_t the_map = REG_REORDER_P({ |
29 | // s8 -> |
30 | {{s8, data_type::undef, 0}, { |
31 | CPU_REORDER_INSTANCE(rnn_weights_reorder_s8_t<s8>) |
32 | CPU_REORDER_INSTANCE(rnn_brgemm_weights_reorder_s8_t<s8, s8>) |
33 | DNNL_X64_ONLY(CPU_REORDER_INSTANCE(x64::brgemm_matmul_matrix_B_reorder_t)) |
34 | |
35 | REG_FAST_DIRECT_COPY(s8, f32) |
36 | REG_FAST_DIRECT_COPY(s8, s32) |
37 | REG_FAST_DIRECT_COPY(s8, bf16) |
38 | REG_FAST_DIRECT_COPY(s8, f16) |
39 | REG_FAST_DIRECT_COPY(s8, s8) |
40 | REG_FAST_DIRECT_COPY(s8, u8) |
41 | |
42 | DNNL_X64_ONLY(CPU_REORDER_INSTANCE(x64::jit_blk_reorder_t)) |
43 | DNNL_X64_ONLY(CPU_REORDER_INSTANCE(x64::jit_uni_reorder_t)) |
44 | |
45 | DNNL_AARCH64_ONLY(CPU_REORDER_INSTANCE(aarch64::jit_blk_reorder_t)) |
46 | DNNL_AARCH64_ONLY(CPU_REORDER_INSTANCE(aarch64::jit_uni_reorder_t)) |
47 | |
48 | DNNL_NON_X64_ONLY(REG_SR_BIDIR(s8, any, f32, nChw16c)) |
49 | DNNL_NON_X64_ONLY(REG_SR_BIDIR(s8, any, s32, nChw16c)) |
50 | DNNL_NON_X64_ONLY(REG_SR_BIDIR(s8, any, bf16, nChw16c)) |
51 | DNNL_NON_X64_ONLY(REG_SR_BIDIR(s8, any, s8, nChw16c)) |
52 | DNNL_NON_X64_ONLY(REG_SR_BIDIR(s8, any, u8, nChw16c)) |
53 | |
54 | DNNL_NON_X64_ONLY(REG_SR_BIDIR(s8, any, f32, OIhw4i16o4i)) |
55 | DNNL_NON_X64_ONLY(REG_SR_BIDIR(s8, any, bf16, OIhw4i16o4i)) |
56 | DNNL_NON_X64_ONLY(REG_SR_BIDIR(s8, any, s8, OIhw4i16o4i)) |
57 | DNNL_NON_X64_ONLY(REG_SR_BIDIR(s8, any, f32, gOIhw4i16o4i)) |
58 | DNNL_NON_X64_ONLY(REG_SR_BIDIR(s8, any, bf16, gOIhw4i16o4i)) |
59 | DNNL_NON_X64_ONLY(REG_SR_BIDIR(s8, any, s8, gOIhw4i16o4i)) |
60 | |
61 | REG_SR(s8, any, f32, any, fmt_order::any, spec::reference) |
62 | REG_SR(s8, any, s32, any, fmt_order::any, spec::reference) |
63 | REG_SR(s8, any, bf16, any, fmt_order::any, spec::reference) |
64 | REG_SR(s8, any, f16, any, fmt_order::any, spec::reference) |
65 | REG_SR(s8, any, s8, any, fmt_order::any, spec::reference) |
66 | REG_SR(s8, any, u8, any, fmt_order::any, spec::reference) |
67 | |
68 | nullptr, |
69 | }}, |
70 | }); |
71 | return the_map; |
72 | } |
73 | |
74 | // clang-format on |
75 | |
76 | } // namespace cpu |
77 | } // namespace impl |
78 | } // namespace dnnl |
79 | |