1/*******************************************************************************
2* Copyright 2021 Intel Corporation
3*
4* Licensed under the Apache License, Version 2.0 (the "License");
5* you may not use this file except in compliance with the License.
6* You may obtain a copy of the License at
7*
8* http://www.apache.org/licenses/LICENSE-2.0
9*
10* Unless required by applicable law or agreed to in writing, software
11* distributed under the License is distributed on an "AS IS" BASIS,
12* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13* See the License for the specific language governing permissions and
14* limitations under the License.
15*******************************************************************************/
16
17#ifndef COMMON_IMPL_REGISTRATION_HPP
18#define COMMON_IMPL_REGISTRATION_HPP
19
20#include "oneapi/dnnl/dnnl_config.h"
21
22// Workload section
23
24// Note: REG_BWD_D_PK is a dedicated macro for deconv to enable bwd_d conv.
25#if BUILD_TRAINING
26#define REG_BWD_PK(...) __VA_ARGS__
27#define REG_BWD_D_PK(...) __VA_ARGS__
28#else
29#define REG_BWD_PK(...) \
30 { nullptr }
31#define REG_BWD_D_PK(...) \
32 { nullptr }
33#endif
34
35// Primitives section
36
37// Note:
38// `_P` is a mandatory suffix for macros. This is to avoid a conflict with
39// `REG_BINARY`, Windows-defined macro.
40
41#if BUILD_PRIMITIVE_ALL || BUILD_BATCH_NORMALIZATION
42#define REG_BNORM_P(...) __VA_ARGS__
43#else
44#define REG_BNORM_P(...) \
45 {}
46#endif
47
48#if BUILD_PRIMITIVE_ALL || BUILD_BINARY
49#define REG_BINARY_P(...) __VA_ARGS__
50#else
51#define REG_BINARY_P(...) \
52 { nullptr }
53#endif
54
55#if BUILD_PRIMITIVE_ALL || BUILD_CONCAT
56#define REG_CONCAT_P(...) __VA_ARGS__
57#else
58#define REG_CONCAT_P(...) \
59 { nullptr }
60#endif
61
62#if BUILD_PRIMITIVE_ALL || BUILD_CONVOLUTION
63#define REG_CONV_P(...) __VA_ARGS__
64#else
65#define REG_CONV_P(...) \
66 {}
67#endif
68
69#if BUILD_PRIMITIVE_ALL || BUILD_DECONVOLUTION
70#define REG_DECONV_P(...) __VA_ARGS__
71// This case is special, it requires handling of convolution_bwd_d internally
72// since major optimizations are based on convolution implementations.
73#ifndef REG_CONV_P
74#error "REG_CONV_P is not defined. Check that convolution is defined prior deconvolution."
75#else
76#undef REG_CONV_P
77#define REG_CONV_P(...) __VA_ARGS__
78#endif
79
80#ifndef REG_BWD_D_PK
81#error "REG_BWD_D_PK is not defined. Dedicated macro was not enabled."
82#else
83#undef REG_BWD_D_PK
84#define REG_BWD_D_PK(...) __VA_ARGS__
85#endif
86
87#else // BUILD_PRIMITIVE_ALL || BUILD_DECONVOLUTION
88#define REG_DECONV_P(...) \
89 {}
90#endif
91
92#if BUILD_PRIMITIVE_ALL || BUILD_ELTWISE
93#define REG_ELTWISE_P(...) __VA_ARGS__
94#else
95#define REG_ELTWISE_P(...) \
96 {}
97#endif
98
99#if BUILD_PRIMITIVE_ALL || BUILD_INNER_PRODUCT
100#define REG_IP_P(...) __VA_ARGS__
101#else
102#define REG_IP_P(...) \
103 {}
104#endif
105
106#if BUILD_PRIMITIVE_ALL || BUILD_LAYER_NORMALIZATION
107#define REG_LNORM_P(...) __VA_ARGS__
108#else
109#define REG_LNORM_P(...) \
110 {}
111#endif
112
113#if BUILD_PRIMITIVE_ALL || BUILD_LRN
114#define REG_LRN_P(...) __VA_ARGS__
115#else
116#define REG_LRN_P(...) \
117 {}
118#endif
119
120#if BUILD_PRIMITIVE_ALL || BUILD_MATMUL
121#define REG_MATMUL_P(...) __VA_ARGS__
122#else
123#define REG_MATMUL_P(...) \
124 { nullptr }
125#endif
126
127#if BUILD_PRIMITIVE_ALL || BUILD_POOLING
128#define REG_POOLING_P(...) __VA_ARGS__
129#else
130#define REG_POOLING_P(...) \
131 {}
132#endif
133
134#if BUILD_PRIMITIVE_ALL || BUILD_PRELU
135#define REG_PRELU_P(...) __VA_ARGS__
136#else
137#define REG_PRELU_P(...) \
138 {}
139#endif
140
141#if BUILD_PRIMITIVE_ALL || BUILD_REDUCTION
142#define REG_REDUCTION_P(...) __VA_ARGS__
143#else
144#define REG_REDUCTION_P(...) \
145 { nullptr }
146#endif
147
148#if BUILD_PRIMITIVE_ALL || BUILD_REORDER
149#define REG_REORDER_P(...) __VA_ARGS__
150#else
151#define REG_REORDER_P(...) \
152 {}
153#endif
154
155#if BUILD_PRIMITIVE_ALL || BUILD_RESAMPLING
156#define REG_RESAMPLING_P(...) __VA_ARGS__
157#else
158#define REG_RESAMPLING_P(...) \
159 {}
160#endif
161
162#if BUILD_PRIMITIVE_ALL || BUILD_RNN
163#define REG_RNN_P(...) __VA_ARGS__
164#else
165#define REG_RNN_P(...) \
166 {}
167#endif
168
169#if BUILD_PRIMITIVE_ALL || BUILD_SHUFFLE
170#define REG_SHUFFLE_P(...) __VA_ARGS__
171#else
172#define REG_SHUFFLE_P(...) \
173 { nullptr }
174#endif
175
176#if BUILD_PRIMITIVE_ALL || BUILD_SOFTMAX
177#define REG_SOFTMAX_P(...) __VA_ARGS__
178#else
179#define REG_SOFTMAX_P(...) \
180 {}
181#endif
182
183#if BUILD_PRIMITIVE_ALL || BUILD_SUM
184#define REG_SUM_P(...) __VA_ARGS__
185#else
186#define REG_SUM_P(...) \
187 { nullptr }
188#endif
189
190// Primitive CPU ISA section is in src/cpu/platform.hpp
191
192#if BUILD_PRIMITIVE_GPU_ISA_ALL || BUILD_GEN9
193#define REG_GEN9_ISA(...) __VA_ARGS__
194#else
195#define REG_GEN9_ISA(...)
196#endif
197
198#if BUILD_PRIMITIVE_GPU_ISA_ALL || BUILD_GEN11
199#define REG_GEN11_ISA(...) __VA_ARGS__
200#else
201#define REG_GEN11_ISA(...)
202#endif
203
204#if BUILD_PRIMITIVE_GPU_ISA_ALL || BUILD_XELP
205#define REG_XELP_ISA(...) __VA_ARGS__
206#else
207#define REG_XELP_ISA(...)
208#endif
209
210#if BUILD_PRIMITIVE_GPU_ISA_ALL || BUILD_XEHP
211#define REG_XEHP_ISA(...) __VA_ARGS__
212#else
213#define REG_XEHP_ISA(...)
214#endif
215
216#if BUILD_PRIMITIVE_GPU_ISA_ALL || BUILD_XEHPG
217#define REG_XEHPG_ISA(...) __VA_ARGS__
218#else
219#define REG_XEHPG_ISA(...)
220#endif
221
222#if BUILD_PRIMITIVE_GPU_ISA_ALL || BUILD_XEHPC
223#define REG_XEHPC_ISA(...) __VA_ARGS__
224#else
225#define REG_XEHPC_ISA(...)
226#endif
227
228#endif
229