1 | /******************************************************************************* |
2 | * Copyright 2020-2022 Intel Corporation |
3 | * |
4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
5 | * you may not use this file except in compliance with the License. |
6 | * You may obtain a copy of the License at |
7 | * |
8 | * http://www.apache.org/licenses/LICENSE-2.0 |
9 | * |
10 | * Unless required by applicable law or agreed to in writing, software |
11 | * distributed under the License is distributed on an "AS IS" BASIS, |
12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
13 | * See the License for the specific language governing permissions and |
14 | * limitations under the License. |
15 | *******************************************************************************/ |
16 | |
17 | #include "cpu/reorder/cpu_reorder.hpp" |
18 | |
19 | namespace dnnl { |
20 | namespace impl { |
21 | namespace cpu { |
22 | |
23 | // clang-format off |
24 | const impl_list_map_t ®ular_bf16_impl_list_map() { |
25 | static const impl_list_map_t the_map = REG_REORDER_P({ |
26 | // bf16 -> |
27 | {{bf16, data_type::undef, 0}, { |
28 | CPU_REORDER_INSTANCE(rnn_weights_reorder_t<bf16, bf16>) |
29 | DNNL_X64_ONLY(CPU_REORDER_INSTANCE(x64::brgemm_matmul_matrix_B_reorder_t)) |
30 | |
31 | DNNL_X64_ONLY(CPU_REORDER_INSTANCE(x64::jit_blk_reorder_t)) |
32 | DNNL_X64_ONLY(CPU_REORDER_INSTANCE(x64::jit_uni_reorder_t)) |
33 | |
34 | DNNL_NON_X64_ONLY(REG_SR_BIDIR(bf16, any, f32, nChw16c)) |
35 | DNNL_NON_X64_ONLY(REG_SR_BIDIR(bf16, any, f32, nCdhw16c)) |
36 | |
37 | DNNL_NON_X64_ONLY(REG_SR_BIDIR(bf16, any, s8, nChw16c)) |
38 | DNNL_NON_X64_ONLY(REG_SR_BIDIR(bf16, any, s8, nCdhw16c)) |
39 | |
40 | DNNL_NON_X64_ONLY(REG_SR_BIDIR(bf16, any, u8, nChw16c)) |
41 | DNNL_NON_X64_ONLY(REG_SR_BIDIR(bf16, any, u8, nCdhw16c)) |
42 | |
43 | DNNL_NON_X64_ONLY(REG_SR_BIDIR(bf16, any, bf16, nChw16c)) |
44 | DNNL_NON_X64_ONLY(REG_SR_BIDIR(bf16, any, bf16, nCdhw16c)) |
45 | |
46 | DNNL_NON_X64_ONLY(REG_SR_BIDIR(bf16, any, f32, OIdhw16o16i)) |
47 | DNNL_NON_X64_ONLY(REG_SR_BIDIR(bf16, any, f32, OIdhw16i16o)) |
48 | |
49 | DNNL_NON_X64_ONLY(REG_SR_BIDIR(bf16, any, s8, OIdhw16o16i)) |
50 | DNNL_NON_X64_ONLY(REG_SR_BIDIR(bf16, any, s8, OIdhw16i16o)) |
51 | |
52 | DNNL_NON_X64_ONLY(REG_SR_BIDIR(bf16, any, u8, OIdhw16o16i)) |
53 | DNNL_NON_X64_ONLY(REG_SR_BIDIR(bf16, any, u8, OIdhw16i16o)) |
54 | |
55 | REG_SR(bf16, any, bf16, any, fmt_order::any, spec::reference) |
56 | REG_SR(bf16, any, f32, any, fmt_order::any, spec::reference) |
57 | REG_SR(bf16, any, s8, any, fmt_order::any, spec::reference) |
58 | REG_SR(bf16, any, u8, any, fmt_order::any, spec::reference) |
59 | |
60 | nullptr, |
61 | }}, |
62 | }); |
63 | return the_map; |
64 | } |
65 | |
66 | // clang-format on |
67 | |
68 | } // namespace cpu |
69 | } // namespace impl |
70 | } // namespace dnnl |
71 | |