1 | /* Copyright 2015 The TensorFlow Authors. All Rights Reserved. |
2 | |
3 | Licensed under the Apache License, Version 2.0 (the "License"); |
4 | you may not use this file except in compliance with the License. |
5 | You may obtain a copy of the License at |
6 | |
7 | http://www.apache.org/licenses/LICENSE-2.0 |
8 | |
9 | Unless required by applicable law or agreed to in writing, software |
10 | distributed under the License is distributed on an "AS IS" BASIS, |
11 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
12 | See the License for the specific language governing permissions and |
13 | limitations under the License. |
14 | ==============================================================================*/ |
15 | |
16 | #include "tensorflow/core/kernels/cwise_ops_common.h" |
17 | |
18 | namespace tensorflow { |
19 | |
20 | // REGISTER# macros ignore all but first type (assumed to be float) when |
21 | // __ANDROID_TYPES_SLIM__ is defined. Since this file is the second of two |
22 | // sharded files, only make its register calls when not __ANDROID_TYPES_SLIM__. |
23 | #if !defined(__ANDROID_TYPES_SLIM__) |
24 | |
25 | REGISTER6(BinaryOp, CPU, "Add" , functor::add, int8, int16, complex64, uint8, |
26 | complex128, tstring); |
27 | |
28 | // Notice: String is excluded to allow marking AddV2 is_commutative and |
29 | // is_aggregate. |
30 | REGISTER8(BinaryOp, CPU, "AddV2" , functor::add, int8, int16, complex64, uint8, |
31 | uint16, uint32, uint64, complex128); |
32 | |
33 | #if GOOGLE_CUDA || TENSORFLOW_USE_ROCM |
34 | #if !defined(MLIR_GENERATED_GPU_KERNELS_ENABLED) |
35 | REGISTER4(BinaryOp, GPU, "Add" , functor::add, uint8, int64, complex64, |
36 | complex128); |
37 | |
38 | REGISTER7(BinaryOp, GPU, "AddV2" , functor::add, uint8, uint16, uint32, uint64, |
39 | int64, complex64, complex128); |
40 | #endif |
41 | |
42 | #endif // GOOGLE_CUDA || TENSORFLOW_USE_ROCM |
43 | |
44 | #endif // !defined(__ANDROID_TYPES_SLIM__) |
45 | |
46 | } // namespace tensorflow |
47 | |