1 | /* automatically generated from ./x86/regs.dat - do not edit */ |
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2 | |
3 | #ifndef NASM_REGS_H |
4 | #define NASM_REGS_H |
5 | |
6 | #define EXPR_REG_START 1 |
7 | |
8 | enum reg_enum { |
9 | R_zero = 0, |
10 | R_none = -1, |
11 | R_AH = EXPR_REG_START, |
12 | R_AL, |
13 | R_AX, |
14 | R_BH, |
15 | R_BL, |
16 | R_BND0, |
17 | R_BND1, |
18 | R_BND2, |
19 | R_BND3, |
20 | R_BP, |
21 | R_BPL, |
22 | R_BX, |
23 | R_CH, |
24 | R_CL, |
25 | R_CR0, |
26 | R_CR1, |
27 | R_CR10, |
28 | R_CR11, |
29 | R_CR12, |
30 | R_CR13, |
31 | R_CR14, |
32 | R_CR15, |
33 | R_CR2, |
34 | R_CR3, |
35 | R_CR4, |
36 | R_CR5, |
37 | R_CR6, |
38 | R_CR7, |
39 | R_CR8, |
40 | R_CR9, |
41 | R_CS, |
42 | R_CX, |
43 | R_DH, |
44 | R_DI, |
45 | R_DIL, |
46 | R_DL, |
47 | R_DR0, |
48 | R_DR1, |
49 | R_DR10, |
50 | R_DR11, |
51 | R_DR12, |
52 | R_DR13, |
53 | R_DR14, |
54 | R_DR15, |
55 | R_DR2, |
56 | R_DR3, |
57 | R_DR4, |
58 | R_DR5, |
59 | R_DR6, |
60 | R_DR7, |
61 | R_DR8, |
62 | R_DR9, |
63 | R_DS, |
64 | R_DX, |
65 | R_EAX, |
66 | R_EBP, |
67 | R_EBX, |
68 | R_ECX, |
69 | R_EDI, |
70 | R_EDX, |
71 | R_ES, |
72 | R_ESI, |
73 | R_ESP, |
74 | R_FS, |
75 | R_GS, |
76 | R_K0, |
77 | R_K1, |
78 | R_K2, |
79 | R_K3, |
80 | R_K4, |
81 | R_K5, |
82 | R_K6, |
83 | R_K7, |
84 | R_MM0, |
85 | R_MM1, |
86 | R_MM2, |
87 | R_MM3, |
88 | R_MM4, |
89 | R_MM5, |
90 | R_MM6, |
91 | R_MM7, |
92 | R_R10, |
93 | R_R10B, |
94 | R_R10D, |
95 | R_R10W, |
96 | R_R11, |
97 | R_R11B, |
98 | R_R11D, |
99 | R_R11W, |
100 | R_R12, |
101 | R_R12B, |
102 | R_R12D, |
103 | R_R12W, |
104 | R_R13, |
105 | R_R13B, |
106 | R_R13D, |
107 | R_R13W, |
108 | R_R14, |
109 | R_R14B, |
110 | R_R14D, |
111 | R_R14W, |
112 | R_R15, |
113 | R_R15B, |
114 | R_R15D, |
115 | R_R15W, |
116 | R_R8, |
117 | R_R8B, |
118 | R_R8D, |
119 | R_R8W, |
120 | R_R9, |
121 | R_R9B, |
122 | R_R9D, |
123 | R_R9W, |
124 | R_RAX, |
125 | R_RBP, |
126 | R_RBX, |
127 | R_RCX, |
128 | R_RDI, |
129 | R_RDX, |
130 | R_RSI, |
131 | R_RSP, |
132 | R_SEGR6, |
133 | R_SEGR7, |
134 | R_SI, |
135 | R_SIL, |
136 | R_SP, |
137 | R_SPL, |
138 | R_SS, |
139 | R_ST0, |
140 | R_ST1, |
141 | R_ST2, |
142 | R_ST3, |
143 | R_ST4, |
144 | R_ST5, |
145 | R_ST6, |
146 | R_ST7, |
147 | R_TR0, |
148 | R_TR1, |
149 | R_TR2, |
150 | R_TR3, |
151 | R_TR4, |
152 | R_TR5, |
153 | R_TR6, |
154 | R_TR7, |
155 | R_XMM0, |
156 | R_XMM1, |
157 | R_XMM10, |
158 | R_XMM11, |
159 | R_XMM12, |
160 | R_XMM13, |
161 | R_XMM14, |
162 | R_XMM15, |
163 | R_XMM16, |
164 | R_XMM17, |
165 | R_XMM18, |
166 | R_XMM19, |
167 | R_XMM2, |
168 | R_XMM20, |
169 | R_XMM21, |
170 | R_XMM22, |
171 | R_XMM23, |
172 | R_XMM24, |
173 | R_XMM25, |
174 | R_XMM26, |
175 | R_XMM27, |
176 | R_XMM28, |
177 | R_XMM29, |
178 | R_XMM3, |
179 | R_XMM30, |
180 | R_XMM31, |
181 | R_XMM4, |
182 | R_XMM5, |
183 | R_XMM6, |
184 | R_XMM7, |
185 | R_XMM8, |
186 | R_XMM9, |
187 | R_YMM0, |
188 | R_YMM1, |
189 | R_YMM10, |
190 | R_YMM11, |
191 | R_YMM12, |
192 | R_YMM13, |
193 | R_YMM14, |
194 | R_YMM15, |
195 | R_YMM16, |
196 | R_YMM17, |
197 | R_YMM18, |
198 | R_YMM19, |
199 | R_YMM2, |
200 | R_YMM20, |
201 | R_YMM21, |
202 | R_YMM22, |
203 | R_YMM23, |
204 | R_YMM24, |
205 | R_YMM25, |
206 | R_YMM26, |
207 | R_YMM27, |
208 | R_YMM28, |
209 | R_YMM29, |
210 | R_YMM3, |
211 | R_YMM30, |
212 | R_YMM31, |
213 | R_YMM4, |
214 | R_YMM5, |
215 | R_YMM6, |
216 | R_YMM7, |
217 | R_YMM8, |
218 | R_YMM9, |
219 | R_ZMM0, |
220 | R_ZMM1, |
221 | R_ZMM10, |
222 | R_ZMM11, |
223 | R_ZMM12, |
224 | R_ZMM13, |
225 | R_ZMM14, |
226 | R_ZMM15, |
227 | R_ZMM16, |
228 | R_ZMM17, |
229 | R_ZMM18, |
230 | R_ZMM19, |
231 | R_ZMM2, |
232 | R_ZMM20, |
233 | R_ZMM21, |
234 | R_ZMM22, |
235 | R_ZMM23, |
236 | R_ZMM24, |
237 | R_ZMM25, |
238 | R_ZMM26, |
239 | R_ZMM27, |
240 | R_ZMM28, |
241 | R_ZMM29, |
242 | R_ZMM3, |
243 | R_ZMM30, |
244 | R_ZMM31, |
245 | R_ZMM4, |
246 | R_ZMM5, |
247 | R_ZMM6, |
248 | R_ZMM7, |
249 | R_ZMM8, |
250 | R_ZMM9, |
251 | REG_ENUM_LIMIT |
252 | }; |
253 | |
254 | #define EXPR_REG_END 240 |
255 | |
256 | #define REG_NUM_AH 4 |
257 | #define REG_NUM_AL 0 |
258 | #define REG_NUM_AX 0 |
259 | #define REG_NUM_BH 7 |
260 | #define REG_NUM_BL 3 |
261 | #define REG_NUM_BND0 0 |
262 | #define REG_NUM_BND1 1 |
263 | #define REG_NUM_BND2 2 |
264 | #define REG_NUM_BND3 3 |
265 | #define REG_NUM_BP 5 |
266 | #define REG_NUM_BPL 5 |
267 | #define REG_NUM_BX 3 |
268 | #define REG_NUM_CH 5 |
269 | #define REG_NUM_CL 1 |
270 | #define REG_NUM_CR0 0 |
271 | #define REG_NUM_CR1 1 |
272 | #define REG_NUM_CR10 10 |
273 | #define REG_NUM_CR11 11 |
274 | #define REG_NUM_CR12 12 |
275 | #define REG_NUM_CR13 13 |
276 | #define REG_NUM_CR14 14 |
277 | #define REG_NUM_CR15 15 |
278 | #define REG_NUM_CR2 2 |
279 | #define REG_NUM_CR3 3 |
280 | #define REG_NUM_CR4 4 |
281 | #define REG_NUM_CR5 5 |
282 | #define REG_NUM_CR6 6 |
283 | #define REG_NUM_CR7 7 |
284 | #define REG_NUM_CR8 8 |
285 | #define REG_NUM_CR9 9 |
286 | #define REG_NUM_CS 1 |
287 | #define REG_NUM_CX 1 |
288 | #define REG_NUM_DH 6 |
289 | #define REG_NUM_DI 7 |
290 | #define REG_NUM_DIL 7 |
291 | #define REG_NUM_DL 2 |
292 | #define REG_NUM_DR0 0 |
293 | #define REG_NUM_DR1 1 |
294 | #define REG_NUM_DR10 10 |
295 | #define REG_NUM_DR11 11 |
296 | #define REG_NUM_DR12 12 |
297 | #define REG_NUM_DR13 13 |
298 | #define REG_NUM_DR14 14 |
299 | #define REG_NUM_DR15 15 |
300 | #define REG_NUM_DR2 2 |
301 | #define REG_NUM_DR3 3 |
302 | #define REG_NUM_DR4 4 |
303 | #define REG_NUM_DR5 5 |
304 | #define REG_NUM_DR6 6 |
305 | #define REG_NUM_DR7 7 |
306 | #define REG_NUM_DR8 8 |
307 | #define REG_NUM_DR9 9 |
308 | #define REG_NUM_DS 3 |
309 | #define REG_NUM_DX 2 |
310 | #define REG_NUM_EAX 0 |
311 | #define REG_NUM_EBP 5 |
312 | #define REG_NUM_EBX 3 |
313 | #define REG_NUM_ECX 1 |
314 | #define REG_NUM_EDI 7 |
315 | #define REG_NUM_EDX 2 |
316 | #define REG_NUM_ES 0 |
317 | #define REG_NUM_ESI 6 |
318 | #define REG_NUM_ESP 4 |
319 | #define REG_NUM_FS 4 |
320 | #define REG_NUM_GS 5 |
321 | #define REG_NUM_K0 0 |
322 | #define REG_NUM_K1 1 |
323 | #define REG_NUM_K2 2 |
324 | #define REG_NUM_K3 3 |
325 | #define REG_NUM_K4 4 |
326 | #define REG_NUM_K5 5 |
327 | #define REG_NUM_K6 6 |
328 | #define REG_NUM_K7 7 |
329 | #define REG_NUM_MM0 0 |
330 | #define REG_NUM_MM1 1 |
331 | #define REG_NUM_MM2 2 |
332 | #define REG_NUM_MM3 3 |
333 | #define REG_NUM_MM4 4 |
334 | #define REG_NUM_MM5 5 |
335 | #define REG_NUM_MM6 6 |
336 | #define REG_NUM_MM7 7 |
337 | #define REG_NUM_R10 10 |
338 | #define REG_NUM_R10B 10 |
339 | #define REG_NUM_R10D 10 |
340 | #define REG_NUM_R10W 10 |
341 | #define REG_NUM_R11 11 |
342 | #define REG_NUM_R11B 11 |
343 | #define REG_NUM_R11D 11 |
344 | #define REG_NUM_R11W 11 |
345 | #define REG_NUM_R12 12 |
346 | #define REG_NUM_R12B 12 |
347 | #define REG_NUM_R12D 12 |
348 | #define REG_NUM_R12W 12 |
349 | #define REG_NUM_R13 13 |
350 | #define REG_NUM_R13B 13 |
351 | #define REG_NUM_R13D 13 |
352 | #define REG_NUM_R13W 13 |
353 | #define REG_NUM_R14 14 |
354 | #define REG_NUM_R14B 14 |
355 | #define REG_NUM_R14D 14 |
356 | #define REG_NUM_R14W 14 |
357 | #define REG_NUM_R15 15 |
358 | #define REG_NUM_R15B 15 |
359 | #define REG_NUM_R15D 15 |
360 | #define REG_NUM_R15W 15 |
361 | #define REG_NUM_R8 8 |
362 | #define REG_NUM_R8B 8 |
363 | #define REG_NUM_R8D 8 |
364 | #define REG_NUM_R8W 8 |
365 | #define REG_NUM_R9 9 |
366 | #define REG_NUM_R9B 9 |
367 | #define REG_NUM_R9D 9 |
368 | #define REG_NUM_R9W 9 |
369 | #define REG_NUM_RAX 0 |
370 | #define REG_NUM_RBP 5 |
371 | #define REG_NUM_RBX 3 |
372 | #define REG_NUM_RCX 1 |
373 | #define REG_NUM_RDI 7 |
374 | #define REG_NUM_RDX 2 |
375 | #define REG_NUM_RSI 6 |
376 | #define REG_NUM_RSP 4 |
377 | #define REG_NUM_SEGR6 6 |
378 | #define REG_NUM_SEGR7 7 |
379 | #define REG_NUM_SI 6 |
380 | #define REG_NUM_SIL 6 |
381 | #define REG_NUM_SP 4 |
382 | #define REG_NUM_SPL 4 |
383 | #define REG_NUM_SS 2 |
384 | #define REG_NUM_ST0 0 |
385 | #define REG_NUM_ST1 1 |
386 | #define REG_NUM_ST2 2 |
387 | #define REG_NUM_ST3 3 |
388 | #define REG_NUM_ST4 4 |
389 | #define REG_NUM_ST5 5 |
390 | #define REG_NUM_ST6 6 |
391 | #define REG_NUM_ST7 7 |
392 | #define REG_NUM_TR0 0 |
393 | #define REG_NUM_TR1 1 |
394 | #define REG_NUM_TR2 2 |
395 | #define REG_NUM_TR3 3 |
396 | #define REG_NUM_TR4 4 |
397 | #define REG_NUM_TR5 5 |
398 | #define REG_NUM_TR6 6 |
399 | #define REG_NUM_TR7 7 |
400 | #define REG_NUM_XMM0 0 |
401 | #define REG_NUM_XMM1 1 |
402 | #define REG_NUM_XMM10 10 |
403 | #define REG_NUM_XMM11 11 |
404 | #define REG_NUM_XMM12 12 |
405 | #define REG_NUM_XMM13 13 |
406 | #define REG_NUM_XMM14 14 |
407 | #define REG_NUM_XMM15 15 |
408 | #define REG_NUM_XMM16 16 |
409 | #define REG_NUM_XMM17 17 |
410 | #define REG_NUM_XMM18 18 |
411 | #define REG_NUM_XMM19 19 |
412 | #define REG_NUM_XMM2 2 |
413 | #define REG_NUM_XMM20 20 |
414 | #define REG_NUM_XMM21 21 |
415 | #define REG_NUM_XMM22 22 |
416 | #define REG_NUM_XMM23 23 |
417 | #define REG_NUM_XMM24 24 |
418 | #define REG_NUM_XMM25 25 |
419 | #define REG_NUM_XMM26 26 |
420 | #define REG_NUM_XMM27 27 |
421 | #define REG_NUM_XMM28 28 |
422 | #define REG_NUM_XMM29 29 |
423 | #define REG_NUM_XMM3 3 |
424 | #define REG_NUM_XMM30 30 |
425 | #define REG_NUM_XMM31 31 |
426 | #define REG_NUM_XMM4 4 |
427 | #define REG_NUM_XMM5 5 |
428 | #define REG_NUM_XMM6 6 |
429 | #define REG_NUM_XMM7 7 |
430 | #define REG_NUM_XMM8 8 |
431 | #define REG_NUM_XMM9 9 |
432 | #define REG_NUM_YMM0 0 |
433 | #define REG_NUM_YMM1 1 |
434 | #define REG_NUM_YMM10 10 |
435 | #define REG_NUM_YMM11 11 |
436 | #define REG_NUM_YMM12 12 |
437 | #define REG_NUM_YMM13 13 |
438 | #define REG_NUM_YMM14 14 |
439 | #define REG_NUM_YMM15 15 |
440 | #define REG_NUM_YMM16 16 |
441 | #define REG_NUM_YMM17 17 |
442 | #define REG_NUM_YMM18 18 |
443 | #define REG_NUM_YMM19 19 |
444 | #define REG_NUM_YMM2 2 |
445 | #define REG_NUM_YMM20 20 |
446 | #define REG_NUM_YMM21 21 |
447 | #define REG_NUM_YMM22 22 |
448 | #define REG_NUM_YMM23 23 |
449 | #define REG_NUM_YMM24 24 |
450 | #define REG_NUM_YMM25 25 |
451 | #define REG_NUM_YMM26 26 |
452 | #define REG_NUM_YMM27 27 |
453 | #define REG_NUM_YMM28 28 |
454 | #define REG_NUM_YMM29 29 |
455 | #define REG_NUM_YMM3 3 |
456 | #define REG_NUM_YMM30 30 |
457 | #define REG_NUM_YMM31 31 |
458 | #define REG_NUM_YMM4 4 |
459 | #define REG_NUM_YMM5 5 |
460 | #define REG_NUM_YMM6 6 |
461 | #define REG_NUM_YMM7 7 |
462 | #define REG_NUM_YMM8 8 |
463 | #define REG_NUM_YMM9 9 |
464 | #define REG_NUM_ZMM0 0 |
465 | #define REG_NUM_ZMM1 1 |
466 | #define REG_NUM_ZMM10 10 |
467 | #define REG_NUM_ZMM11 11 |
468 | #define REG_NUM_ZMM12 12 |
469 | #define REG_NUM_ZMM13 13 |
470 | #define REG_NUM_ZMM14 14 |
471 | #define REG_NUM_ZMM15 15 |
472 | #define REG_NUM_ZMM16 16 |
473 | #define REG_NUM_ZMM17 17 |
474 | #define REG_NUM_ZMM18 18 |
475 | #define REG_NUM_ZMM19 19 |
476 | #define REG_NUM_ZMM2 2 |
477 | #define REG_NUM_ZMM20 20 |
478 | #define REG_NUM_ZMM21 21 |
479 | #define REG_NUM_ZMM22 22 |
480 | #define REG_NUM_ZMM23 23 |
481 | #define REG_NUM_ZMM24 24 |
482 | #define REG_NUM_ZMM25 25 |
483 | #define REG_NUM_ZMM26 26 |
484 | #define REG_NUM_ZMM27 27 |
485 | #define REG_NUM_ZMM28 28 |
486 | #define REG_NUM_ZMM29 29 |
487 | #define REG_NUM_ZMM3 3 |
488 | #define REG_NUM_ZMM30 30 |
489 | #define REG_NUM_ZMM31 31 |
490 | #define REG_NUM_ZMM4 4 |
491 | #define REG_NUM_ZMM5 5 |
492 | #define REG_NUM_ZMM6 6 |
493 | #define REG_NUM_ZMM7 7 |
494 | #define REG_NUM_ZMM8 8 |
495 | #define REG_NUM_ZMM9 9 |
496 | |
497 | |
498 | #endif /* NASM_REGS_H */ |
499 |