1/* This file is auto-generated. Don't edit. */
2#ifndef NASM_IFLAGGEN_H
3#define NASM_IFLAGGEN_H 1
4
5#define IF_SM 0 /* Size match */
6#define IF_SM2 1 /* Size match first two operands */
7#define IF_SB 2 /* Unsized operands can't be non-byte */
8#define IF_SW 3 /* Unsized operands can't be non-word */
9#define IF_SD 4 /* Unsized operands can't be non-dword */
10#define IF_SQ 5 /* Unsized operands can't be non-qword */
11#define IF_SO 6 /* Unsized operands can't be non-oword */
12#define IF_SY 7 /* Unsized operands can't be non-yword */
13#define IF_SZ 8 /* Unsized operands can't be non-zword */
14#define IF_SIZE 9 /* Unsized operands must match the bitsize */
15#define IF_SX 10 /* Unsized operands not allowed */
16#define IF_AR0 11 /* SB, SW, SD applies to argument 0 */
17#define IF_AR1 12 /* SB, SW, SD applies to argument 1 */
18#define IF_AR2 13 /* SB, SW, SD applies to argument 2 */
19#define IF_AR3 14 /* SB, SW, SD applies to argument 3 */
20#define IF_AR4 15 /* SB, SW, SD applies to argument 4 */
21#define IF_OPT 16 /* Optimizing assembly only */
22 /* 17...31 unused */
23#define IF_PRIV 32 /* Privileged instruction */
24#define IF_SMM 33 /* Only valid in SMM */
25#define IF_PROT 34 /* Protected mode only */
26#define IF_LOCK 35 /* Lockable if operand 0 is memory */
27#define IF_NOLONG 36 /* Not available in long mode */
28#define IF_LONG 37 /* Long mode */
29#define IF_NOHLE 38 /* HLE prefixes forbidden */
30#define IF_MIB 39 /* disassemble with split EA */
31#define IF_BND 40 /* BND (0xF2) prefix available */
32#define IF_UNDOC 41 /* Undocumented */
33#define IF_HLE 42 /* HLE prefixed */
34#define IF_FPU 43 /* FPU */
35#define IF_MMX 44 /* MMX */
36#define IF_3DNOW 45 /* 3DNow! */
37#define IF_SSE 46 /* SSE (KNI, MMX2) */
38#define IF_SSE2 47 /* SSE2 */
39#define IF_SSE3 48 /* SSE3 (PNI) */
40#define IF_VMX 49 /* VMX */
41#define IF_SSSE3 50 /* SSSE3 */
42#define IF_SSE4A 51 /* AMD SSE4a */
43#define IF_SSE41 52 /* SSE4.1 */
44#define IF_SSE42 53 /* SSE4.2 */
45#define IF_SSE5 54 /* SSE5 */
46#define IF_AVX 55 /* AVX (256-bit floating point) */
47#define IF_AVX2 56 /* AVX2 (256-bit integer) */
48#define IF_FMA 57 /* */
49#define IF_BMI1 58 /* */
50#define IF_BMI2 59 /* */
51#define IF_TBM 60 /* */
52#define IF_RTM 61 /* */
53#define IF_INVPCID 62 /* */
54#define IF_AVX512 63 /* AVX-512F (512-bit base architecture) */
55#define IF_AVX512CD 64 /* AVX-512 Conflict Detection */
56#define IF_AVX512ER 65 /* AVX-512 Exponential and Reciprocal */
57#define IF_AVX512PF 66 /* AVX-512 Prefetch */
58#define IF_MPX 67 /* MPX */
59#define IF_SHA 68 /* SHA */
60#define IF_PREFETCHWT1 69 /* PREFETCHWT1 */
61#define IF_AVX512VL 70 /* AVX-512 Vector Length Orthogonality */
62#define IF_AVX512DQ 71 /* AVX-512 Dword and Qword */
63#define IF_AVX512BW 72 /* AVX-512 Byte and Word */
64#define IF_AVX512IFMA 73 /* AVX-512 IFMA instructions */
65#define IF_AVX512VBMI 74 /* AVX-512 VBMI instructions */
66#define IF_AES 75 /* AES instructions */
67#define IF_VAES 76 /* AES AVX instructions */
68#define IF_VPCLMULQDQ 77 /* AVX Carryless Multiplication */
69#define IF_GFNI 78 /* Galois Field instructions */
70#define IF_AVX512VBMI2 79 /* AVX-512 VBMI2 instructions */
71#define IF_AVX512VNNI 80 /* AVX-512 VNNI instructions */
72#define IF_AVX512BITALG 81 /* AVX-512 Bit Algorithm instructions */
73#define IF_AVX512VPOPCNTDQ 82 /* AVX-512 VPOPCNTD/VPOPCNTQ */
74#define IF_AVX5124FMAPS 83 /* AVX-512 4-iteration multiply-add */
75#define IF_AVX5124VNNIW 84 /* AVX-512 4-iteration dot product */
76#define IF_SGX 85 /* Intel Software Guard Extensions (SGX) */
77#define IF_OBSOLETE 86 /* Instruction removed from architecture */
78#define IF_VEX 87 /* VEX or XOP encoded instruction */
79#define IF_EVEX 88 /* EVEX encoded instruction */
80 /* 89...95 unused */
81#define IF_8086 96 /* 8086 */
82#define IF_186 97 /* 186+ */
83#define IF_286 98 /* 286+ */
84#define IF_386 99 /* 386+ */
85#define IF_486 100 /* 486+ */
86#define IF_PENT 101 /* Pentium */
87#define IF_P6 102 /* P6 */
88#define IF_KATMAI 103 /* Katmai */
89#define IF_WILLAMETTE 104 /* Willamette */
90#define IF_PRESCOTT 105 /* Prescott */
91#define IF_X86_64 106 /* x86-64 (long or legacy mode) */
92#define IF_NEHALEM 107 /* Nehalem */
93#define IF_WESTMERE 108 /* Westmere */
94#define IF_SANDYBRIDGE 109 /* Sandy Bridge */
95#define IF_FUTURE 110 /* Future processor (not yet disclosed) */
96#define IF_IA64 111 /* IA64 (in x86 mode) */
97#define IF_CYRIX 112 /* Cyrix-specific */
98#define IF_AMD 113 /* AMD-specific */
99
100#define IF_FIELD_COUNT 4
101typedef struct {
102 uint32_t field[IF_FIELD_COUNT];
103} iflag_t;
104
105extern const iflag_t insns_flags[265];
106
107#endif /* NASM_IFLAGGEN_H */
108