1 | #include <stdint.h> |
2 | |
3 | #include <cpuinfo.h> |
4 | #include <x86/api.h> |
5 | |
6 | |
7 | /* Intel vendor string: "GenuineIntel" */ |
8 | #define Genu UINT32_C(0x756E6547) |
9 | #define ineI UINT32_C(0x49656E69) |
10 | #define ntel UINT32_C(0x6C65746E) |
11 | |
12 | /* AMD vendor strings: "AuthenticAMD", "AMDisbetter!", "AMD ISBETTER" */ |
13 | #define Auth UINT32_C(0x68747541) |
14 | #define enti UINT32_C(0x69746E65) |
15 | #define cAMD UINT32_C(0x444D4163) |
16 | #define AMDi UINT32_C(0x69444D41) |
17 | #define sbet UINT32_C(0x74656273) |
18 | #define ter UINT32_C(0x21726574) |
19 | #define AMD UINT32_C(0x20444D41) |
20 | #define ISBE UINT32_C(0x45425349) |
21 | #define TTER UINT32_C(0x52455454) |
22 | |
23 | /* VIA (Centaur) vendor strings: "CentaurHauls", "VIA VIA VIA " */ |
24 | #define Cent UINT32_C(0x746E6543) |
25 | #define aurH UINT32_C(0x48727561) |
26 | #define auls UINT32_C(0x736C7561) |
27 | #define VIA UINT32_C(0x20414956) |
28 | |
29 | /* Hygon vendor string: "HygonGenuine" */ |
30 | #define Hygo UINT32_C(0x6F677948) |
31 | #define nGen UINT32_C(0x6E65476E) |
32 | #define uine UINT32_C(0x656E6975) |
33 | |
34 | /* Transmeta vendor strings: "GenuineTMx86", "TransmetaCPU" */ |
35 | #define ineT UINT32_C(0x54656E69) |
36 | #define Mx86 UINT32_C(0x3638784D) |
37 | #define Tran UINT32_C(0x6E617254) |
38 | #define smet UINT32_C(0x74656D73) |
39 | #define aCPU UINT32_C(0x55504361) |
40 | |
41 | /* Cyrix vendor string: "CyrixInstead" */ |
42 | #define Cyri UINT32_C(0x69727943) |
43 | #define xIns UINT32_C(0x736E4978) |
44 | #define tead UINT32_C(0x64616574) |
45 | |
46 | /* Rise vendor string: "RiseRiseRise" */ |
47 | #define Rise UINT32_C(0x65736952) |
48 | |
49 | /* NSC vendor string: "Geode by NSC" */ |
50 | #define Geod UINT32_C(0x646F6547) |
51 | #define e_by UINT32_C(0x79622065) |
52 | #define NSC UINT32_C(0x43534E20) |
53 | |
54 | /* SiS vendor string: "SiS SiS SiS " */ |
55 | #define SiS UINT32_C(0x20536953) |
56 | |
57 | /* NexGen vendor string: "NexGenDriven" */ |
58 | #define NexG UINT32_C(0x4778654E) |
59 | #define enDr UINT32_C(0x72446E65) |
60 | #define iven UINT32_C(0x6E657669) |
61 | |
62 | /* UMC vendor string: "UMC UMC UMC " */ |
63 | #define UMC UINT32_C(0x20434D55) |
64 | |
65 | /* RDC vendor string: "Genuine RDC" */ |
66 | #define ine UINT32_C(0x20656E69) |
67 | #define RDC UINT32_C(0x43445220) |
68 | |
69 | /* D&MP vendor string: "Vortex86 SoC" */ |
70 | #define Vort UINT32_C(0x74726F56) |
71 | #define ex86 UINT32_C(0x36387865) |
72 | #define SoC UINT32_C(0x436F5320) |
73 | |
74 | |
75 | enum cpuinfo_vendor cpuinfo_x86_decode_vendor(uint32_t ebx, uint32_t ecx, uint32_t edx) { |
76 | switch (ebx) { |
77 | case Genu: |
78 | switch (edx) { |
79 | case ineI: |
80 | if (ecx == ntel) { |
81 | /* "GenuineIntel" */ |
82 | return cpuinfo_vendor_intel; |
83 | } |
84 | break; |
85 | #if CPUINFO_ARCH_X86 |
86 | case ineT: |
87 | if (ecx == Mx86) { |
88 | /* "GenuineTMx86" */ |
89 | return cpuinfo_vendor_transmeta; |
90 | } |
91 | break; |
92 | case ine: |
93 | if (ecx == RDC) { |
94 | /* "Genuine RDC" */ |
95 | return cpuinfo_vendor_rdc; |
96 | } |
97 | break; |
98 | #endif |
99 | } |
100 | break; |
101 | case Auth: |
102 | if (edx == enti && ecx == cAMD) { |
103 | /* "AuthenticAMD" */ |
104 | return cpuinfo_vendor_amd; |
105 | } |
106 | break; |
107 | case Cent: |
108 | if (edx == aurH && ecx == auls) { |
109 | /* "CentaurHauls" */ |
110 | return cpuinfo_vendor_via; |
111 | } |
112 | break; |
113 | case Hygo: |
114 | if (edx == nGen && ecx == uine) { |
115 | /* "HygonGenuine" */ |
116 | return cpuinfo_vendor_hygon; |
117 | } |
118 | break; |
119 | #if CPUINFO_ARCH_X86 |
120 | case AMDi: |
121 | if (edx == sbet && ecx == ter) { |
122 | /* "AMDisbetter!" */ |
123 | return cpuinfo_vendor_amd; |
124 | } |
125 | break; |
126 | case AMD: |
127 | if (edx == ISBE && ecx == TTER) { |
128 | /* "AMD ISBETTER" */ |
129 | return cpuinfo_vendor_amd; |
130 | } |
131 | break; |
132 | case VIA: |
133 | if (edx == VIA && ecx == VIA) { |
134 | /* "VIA VIA VIA " */ |
135 | return cpuinfo_vendor_via; |
136 | } |
137 | break; |
138 | case Tran: |
139 | if (edx == smet && ecx == aCPU) { |
140 | /* "TransmetaCPU" */ |
141 | return cpuinfo_vendor_transmeta; |
142 | } |
143 | break; |
144 | case Cyri: |
145 | if (edx == xIns && ecx == tead) { |
146 | /* "CyrixInstead" */ |
147 | return cpuinfo_vendor_cyrix; |
148 | } |
149 | break; |
150 | case Rise: |
151 | if (edx == Rise && ecx == Rise) { |
152 | /* "RiseRiseRise" */ |
153 | return cpuinfo_vendor_rise; |
154 | } |
155 | break; |
156 | case Geod: |
157 | if (edx == e_by && ecx == NSC) { |
158 | /* "Geode by NSC" */ |
159 | return cpuinfo_vendor_nsc; |
160 | } |
161 | break; |
162 | case SiS: |
163 | if (edx == SiS && ecx == SiS) { |
164 | /* "SiS SiS SiS " */ |
165 | return cpuinfo_vendor_sis; |
166 | } |
167 | break; |
168 | case NexG: |
169 | if (edx == enDr && ecx == iven) { |
170 | /* "NexGenDriven" */ |
171 | return cpuinfo_vendor_nexgen; |
172 | } |
173 | break; |
174 | case UMC: |
175 | if (edx == UMC && ecx == UMC) { |
176 | /* "UMC UMC UMC " */ |
177 | return cpuinfo_vendor_umc; |
178 | } |
179 | break; |
180 | case Vort: |
181 | if (edx == ex86 && ecx == SoC) { |
182 | /* "Vortex86 SoC" */ |
183 | return cpuinfo_vendor_dmp; |
184 | } |
185 | break; |
186 | #endif |
187 | } |
188 | return cpuinfo_vendor_unknown; |
189 | } |
190 | |