1// required for old g++ to compile PRId64 macros, see
2// https://github.com/pytorch/pytorch/issues/3571
3// for context
4#ifndef __STDC_FORMAT_MACROS
5#define __STDC_FORMAT_MACROS
6#endif
7
8// an external backend might generate file within its code tree
9// and check all the source files within the tree with clang-format.
10// so, disable it since the backend might have a different config.
11// clang-format off
12
13// NOTE: This condition is true for all PyTorch internal libraries, it
14// just excludes external projects such as torch_xla which
15// re-use some of the PyTorch codegen machinery.
16#if defined(CAFFE2_BUILD_MAIN_LIB) || \
17 defined(TORCH_CUDA_BUILD_MAIN_LIB) || \
18 defined(TORCH_HIP_BUILD_MAIN_LIB) || \
19 defined(TORCH_CUDA_CU_BUILD_MAIN_LIB) || \
20 defined(TORCH_CUDA_CPP_BUILD_MAIN_LIB)
21#define TORCH_ASSERT_ONLY_METHOD_OPERATORS
22#endif
23
24// @generated by torchgen/gen.py from RegisterDispatchKey.cpp
25
26#include <c10/core/TensorImpl.h>
27#include <c10/core/Allocator.h>
28#include <ATen/DeviceGuard.h>
29#include <ATen/NamedTensorUtils.h>
30#include <ATen/Utils.h>
31#include <ATen/WrapDimUtils.h>
32#include <ATen/Dispatch.h>
33#include <c10/util/ExclusivelyOwned.h>
34#include <c10/util/Half.h>
35#include <c10/core/UndefinedTensorImpl.h>
36#include <c10/util/Optional.h>
37#include <ATen/Tensor.h>
38#include <ATen/native/Resize.h>
39
40#include <cstddef>
41#include <functional>
42#include <memory>
43#include <utility>
44
45#include <ATen/Config.h>
46#include <ATen/core/op_registration/adaption.h>
47#include <torch/library.h>
48
49
50#include <ATen/ops/as_strided_native.h>
51#include <ATen/ops/empty.h>
52#include <ATen/ops/empty_strided.h>
53#include <ATen/ops/_copy_from_and_resize.h>
54#include <ATen/ops/_copy_from.h>
55#include <ATen/ops/_mkldnn_reshape_native.h>
56#include <ATen/ops/_mkldnn_transpose_native.h>
57#include <ATen/ops/_native_batch_norm_legit_native.h>
58#include <ATen/ops/_prelu_kernel_backward_native.h>
59#include <ATen/ops/_prelu_kernel_native.h>
60#include <ATen/ops/_softmax_native.h>
61#include <ATen/ops/_to_dense_native.h>
62#include <ATen/ops/adaptive_avg_pool2d_native.h>
63#include <ATen/ops/add_native.h>
64#include <ATen/ops/avg_pool2d_backward_native.h>
65#include <ATen/ops/avg_pool2d_native.h>
66#include <ATen/ops/avg_pool3d_backward_native.h>
67#include <ATen/ops/avg_pool3d_native.h>
68#include <ATen/ops/clone_native.h>
69#include <ATen/ops/copy_native.h>
70#include <ATen/ops/empty_native.h>
71#include <ATen/ops/gelu_backward_native.h>
72#include <ATen/ops/gelu_native.h>
73#include <ATen/ops/mkldnn_adaptive_avg_pool2d_backward_native.h>
74#include <ATen/ops/mkldnn_adaptive_avg_pool2d_native.h>
75#include <ATen/ops/mkldnn_linear_backward_input_native.h>
76#include <ATen/ops/mkldnn_linear_backward_native.h>
77#include <ATen/ops/mkldnn_linear_backward_weights_native.h>
78#include <ATen/ops/mkldnn_linear_native.h>
79#include <ATen/ops/mkldnn_max_pool2d_backward_native.h>
80#include <ATen/ops/mkldnn_max_pool2d_native.h>
81#include <ATen/ops/mkldnn_max_pool3d_backward_native.h>
82#include <ATen/ops/mkldnn_max_pool3d_native.h>
83#include <ATen/ops/mkldnn_reorder_conv2d_weight_native.h>
84#include <ATen/ops/mkldnn_reorder_conv3d_weight_native.h>
85#include <ATen/ops/mul_native.h>
86#include <ATen/ops/native_batch_norm_backward_native.h>
87#include <ATen/ops/native_batch_norm_native.h>
88#include <ATen/ops/relu_native.h>
89#include <ATen/ops/sigmoid_native.h>
90#include <ATen/ops/tanh_native.h>
91#include <ATen/ops/threshold_backward_native.h>
92#include <ATen/ops/view_native.h>
93#include <ATen/ops/zero_native.h>
94
95// See template file RegisterDispatchDefinitions.ini
96namespace at {
97// NB: TORCH_LIBRARY_IMPL must be in an anonymous namespace to avoid
98// ambiguity with conflicting identifiers that may have been defined in
99// at namespace already.
100namespace {
101void resize_out(const Tensor &out, IntArrayRef sizes, IntArrayRef strides, const TensorOptions &options) {
102 TORCH_CHECK(options.dtype() == out.dtype(),
103 "Expected out tensor to have dtype ", options.dtype(), ", but got ", out.dtype(), " instead");
104 TORCH_CHECK(options.device() == out.device(),
105 "Expected out tensor to have device ", options.device(), ", but got ", out.device(), " instead");
106 const bool resized = at::native::resize_output(out, sizes);
107 // Only restride if a resize occurred; otherwise we ignore the (advisory)
108 // strides from the meta function and directly use the output tensor's
109 // preexisting strides
110 if (resized) {
111 if (!strides.empty()) {
112 TORCH_INTERNAL_ASSERT(!options.memory_format_opt().has_value());
113 // TODO: avoid the redispatch here
114 out.as_strided_(sizes, strides);
115 } else if (options.memory_format_opt().has_value()) {
116 out.unsafeGetTensorImpl()->empty_tensor_restride(*options.memory_format_opt());
117 }
118 }
119}
120void check_inplace(const Tensor &self, IntArrayRef sizes, const TensorOptions &options) {
121 // These checks are needed on those operators that:
122 // 1) don't use 'TensorIterator' (e.g. 'addmm' and 'baddbmm')
123 // 2) have particular typing rules (e.g. 'cumsum' and 'cumprod')
124 // For other operators (e.g. 'add'), 'TensorIterator' already checks
125 // these things separately.
126 TORCH_CHECK(options.dtype() == self.dtype(),
127 "Bad in-place call: ",
128 "input tensor dtype ", self.dtype(), " and output tensor dtype ", options.dtype(), " should match");
129 TORCH_CHECK(options.device() == self.device(),
130 "Bad in-place call: ",
131 "input tensor device ", self.device(), " and output tensor device ", options.device(), " should match");
132 TORCH_CHECK(sizes == self.sizes(),
133 "Bad in-place call: ",
134 "input tensor size ", self.sizes(), " and output tensor size ", sizes, " should match");
135}
136namespace {
137at::Tensor wrapper_MkldnnCPU_Tensor_add(const at::Tensor & self, const at::Tensor & other, const at::Scalar & alpha) {
138 // No device check
139 // DeviceGuard omitted
140 return at::native::mkldnn_add(self, other, alpha);
141}
142} // anonymous namespace
143namespace {
144at::Tensor & wrapper_MkldnnCPU_out_add_out(const at::Tensor & self, const at::Tensor & other, const at::Scalar & alpha, at::Tensor & out) {
145 // No device check
146 // DeviceGuard omitted
147 return at::native::mkldnn_add_out(self, other, alpha, out);
148}
149} // anonymous namespace
150namespace {
151at::Tensor & wrapper_MkldnnCPU_Tensor_add_(at::Tensor & self, const at::Tensor & other, const at::Scalar & alpha) {
152 // No device check
153 // DeviceGuard omitted
154 return at::native::mkldnn_add_(self, other, alpha);
155}
156} // anonymous namespace
157namespace {
158at::Tensor & wrapper_MkldnnCPU__copy_(at::Tensor & self, const at::Tensor & src, bool non_blocking) {
159 // No device check
160 // DeviceGuard omitted
161 return at::native::copy_mkldnn_(self, src, non_blocking);
162}
163} // anonymous namespace
164namespace {
165at::Tensor wrapper_MkldnnCPU_memory_format_empty(c10::SymIntArrayRef size, c10::optional<at::ScalarType> dtype, c10::optional<at::Layout> layout, c10::optional<at::Device> device, c10::optional<bool> pin_memory, c10::optional<at::MemoryFormat> memory_format) {
166 // No device check
167 // DeviceGuard omitted
168 return at::native::empty_mkldnn(C10_AS_INTARRAYREF_SLOW(size), dtype, layout, device, pin_memory, memory_format);
169}
170} // anonymous namespace
171namespace {
172at::Tensor wrapper_MkldnnCPU__mkldnn_linear(const at::Tensor & self, const at::Tensor & weight, const c10::optional<at::Tensor> & bias) {
173 // No device check
174 // DeviceGuard omitted
175 return at::native::mkldnn_linear(self, weight, bias);
176}
177} // anonymous namespace
178namespace {
179at::Tensor wrapper_MkldnnCPU__mkldnn_linear_backward_input(at::IntArrayRef input_size, const at::Tensor & grad_output, const at::Tensor & weight) {
180 // No device check
181 // DeviceGuard omitted
182 return at::native::mkldnn_linear_backward_input(input_size, grad_output, weight);
183}
184} // anonymous namespace
185namespace {
186::std::tuple<at::Tensor,at::Tensor> wrapper_MkldnnCPU__mkldnn_linear_backward_weights(const at::Tensor & grad_output, const at::Tensor & input, const at::Tensor & weight, bool bias_defined) {
187 // No device check
188 // DeviceGuard omitted
189 return at::native::mkldnn_linear_backward_weights(grad_output, input, weight, bias_defined);
190}
191} // anonymous namespace
192namespace {
193::std::tuple<at::Tensor,at::Tensor,at::Tensor> wrapper_MkldnnCPU__mkldnn_linear_backward(const at::Tensor & self, const at::Tensor & grad_output, const at::Tensor & weight, ::std::array<bool,3> output_mask) {
194 // No device check
195 // DeviceGuard omitted
196 return at::native::mkldnn_linear_backward(self, grad_output, weight, output_mask);
197}
198} // anonymous namespace
199namespace {
200at::Tensor wrapper_MkldnnCPU__mkldnn_max_pool2d(const at::Tensor & self, at::IntArrayRef kernel_size, at::IntArrayRef stride, at::IntArrayRef padding, at::IntArrayRef dilation, bool ceil_mode) {
201 // No device check
202 // DeviceGuard omitted
203 return at::native::mkldnn_max_pool2d(self, kernel_size, stride, padding, dilation, ceil_mode);
204}
205} // anonymous namespace
206namespace {
207at::Tensor wrapper_MkldnnCPU__mkldnn_max_pool2d_backward(const at::Tensor & grad_output, const at::Tensor & output, const at::Tensor & input, at::IntArrayRef kernel_size, at::IntArrayRef stride, at::IntArrayRef padding, at::IntArrayRef dilation, bool ceil_mode) {
208 // No device check
209 // DeviceGuard omitted
210 return at::native::mkldnn_max_pool2d_backward(grad_output, output, input, kernel_size, stride, padding, dilation, ceil_mode);
211}
212} // anonymous namespace
213namespace {
214at::Tensor wrapper_MkldnnCPU__mkldnn_max_pool3d(const at::Tensor & self, at::IntArrayRef kernel_size, at::IntArrayRef stride, at::IntArrayRef padding, at::IntArrayRef dilation, bool ceil_mode) {
215 // No device check
216 // DeviceGuard omitted
217 return at::native::mkldnn_max_pool3d(self, kernel_size, stride, padding, dilation, ceil_mode);
218}
219} // anonymous namespace
220namespace {
221at::Tensor wrapper_MkldnnCPU__mkldnn_max_pool3d_backward(const at::Tensor & grad_output, const at::Tensor & output, const at::Tensor & input, at::IntArrayRef kernel_size, at::IntArrayRef stride, at::IntArrayRef padding, at::IntArrayRef dilation, bool ceil_mode) {
222 // No device check
223 // DeviceGuard omitted
224 return at::native::mkldnn_max_pool3d_backward(grad_output, output, input, kernel_size, stride, padding, dilation, ceil_mode);
225}
226} // anonymous namespace
227namespace {
228at::Tensor wrapper_MkldnnCPU_Tensor_mul(const at::Tensor & self, const at::Tensor & other) {
229 // No device check
230 // DeviceGuard omitted
231 return at::native::mkldnn_mul(self, other);
232}
233} // anonymous namespace
234namespace {
235at::Tensor & wrapper_MkldnnCPU_out_mul_out(const at::Tensor & self, const at::Tensor & other, at::Tensor & out) {
236 // No device check
237 // DeviceGuard omitted
238 return at::native::mkldnn_mul_out(self, other, out);
239}
240} // anonymous namespace
241namespace {
242at::Tensor & wrapper_MkldnnCPU_Tensor_mul_(at::Tensor & self, const at::Tensor & other) {
243 // No device check
244 // DeviceGuard omitted
245 return at::native::mkldnn_mul_(self, other);
246}
247} // anonymous namespace
248namespace {
249::std::tuple<at::Tensor,at::Tensor,at::Tensor> wrapper_MkldnnCPU__native_batch_norm(const at::Tensor & input, const c10::optional<at::Tensor> & weight, const c10::optional<at::Tensor> & bias, const c10::optional<at::Tensor> & running_mean, const c10::optional<at::Tensor> & running_var, bool training, double momentum, double eps) {
250 // No device check
251 // DeviceGuard omitted
252 return at::native::mkldnn_batch_norm(input, weight, bias, running_mean, running_var, training, momentum, eps);
253}
254} // anonymous namespace
255namespace {
256::std::tuple<at::Tensor,at::Tensor,at::Tensor> wrapper_MkldnnCPU___native_batch_norm_legit(const at::Tensor & input, const c10::optional<at::Tensor> & weight, const c10::optional<at::Tensor> & bias, at::Tensor & running_mean, at::Tensor & running_var, bool training, double momentum, double eps) {
257 // No device check
258 // DeviceGuard omitted
259 return at::native::_mkldnn_batch_norm_legit(input, weight, bias, running_mean, running_var, training, momentum, eps);
260}
261} // anonymous namespace
262namespace {
263::std::tuple<at::Tensor,at::Tensor,at::Tensor> wrapper_MkldnnCPU_no_stats__native_batch_norm_legit(const at::Tensor & input, const c10::optional<at::Tensor> & weight, const c10::optional<at::Tensor> & bias, bool training, double momentum, double eps) {
264 // No device check
265 // DeviceGuard omitted
266 return at::native::_mkldnn_batch_norm_legit_no_stats(input, weight, bias, training, momentum, eps);
267}
268} // anonymous namespace
269namespace {
270::std::tuple<at::Tensor,at::Tensor,at::Tensor> wrapper_MkldnnCPU__native_batch_norm_backward(const at::Tensor & grad_out, const at::Tensor & input, const c10::optional<at::Tensor> & weight, const c10::optional<at::Tensor> & running_mean, const c10::optional<at::Tensor> & running_var, const c10::optional<at::Tensor> & save_mean, const c10::optional<at::Tensor> & save_invstd, bool train, double eps, ::std::array<bool,3> output_mask) {
271 // No device check
272 // DeviceGuard omitted
273 return at::native::mkldnn_batch_norm_backward(grad_out, input, weight, running_mean, running_var, save_mean, save_invstd, train, eps, output_mask);
274}
275} // anonymous namespace
276namespace {
277at::Tensor wrapper_MkldnnCPU___mkldnn_reshape(const at::Tensor & self, at::IntArrayRef shape) {
278 // No device check
279 // DeviceGuard omitted
280 return at::native::mkldnn_reshape(self, shape);
281}
282} // anonymous namespace
283namespace {
284at::Tensor wrapper_MkldnnCPU__relu(const at::Tensor & self) {
285 // No device check
286 // DeviceGuard omitted
287 return at::native::mkldnn_relu(self);
288}
289} // anonymous namespace
290namespace {
291at::Tensor & wrapper_MkldnnCPU__relu_(at::Tensor & self) {
292 // No device check
293 // DeviceGuard omitted
294 return at::native::mkldnn_relu_(self);
295}
296} // anonymous namespace
297namespace {
298at::Tensor wrapper_MkldnnCPU___prelu_kernel(const at::Tensor & self, const at::Tensor & weight) {
299 // No device check
300 // DeviceGuard omitted
301 return at::native::mkldnn_prelu(self, weight);
302}
303} // anonymous namespace
304namespace {
305::std::tuple<at::Tensor,at::Tensor> wrapper_MkldnnCPU___prelu_kernel_backward(const at::Tensor & grad_output, const at::Tensor & self, const at::Tensor & weight) {
306 // No device check
307 // DeviceGuard omitted
308 return at::native::mkldnn_prelu_backward(grad_output, self, weight);
309}
310} // anonymous namespace
311namespace {
312at::Tensor wrapper_MkldnnCPU__gelu(const at::Tensor & self, c10::string_view approximate) {
313 // No device check
314 // DeviceGuard omitted
315 return at::native::mkldnn_gelu(self, approximate);
316}
317} // anonymous namespace
318namespace {
319at::Tensor wrapper_MkldnnCPU__gelu_backward(const at::Tensor & grad_output, const at::Tensor & self, c10::string_view approximate) {
320 // No device check
321 // DeviceGuard omitted
322 return at::native::mkldnn_gelu_backward(grad_output, self, approximate);
323}
324} // anonymous namespace
325namespace {
326at::Tensor wrapper_MkldnnCPU__sigmoid(const at::Tensor & self) {
327 // No device check
328 // DeviceGuard omitted
329 return at::native::mkldnn_sigmoid(self);
330}
331} // anonymous namespace
332namespace {
333at::Tensor & wrapper_MkldnnCPU__sigmoid_(at::Tensor & self) {
334 // No device check
335 // DeviceGuard omitted
336 return at::native::mkldnn_sigmoid_(self);
337}
338} // anonymous namespace
339namespace {
340at::Tensor wrapper_MkldnnCPU___softmax(const at::Tensor & self, int64_t dim, bool half_to_float) {
341 // No device check
342 // DeviceGuard omitted
343 return at::native::mkldnn_softmax(self, dim, half_to_float);
344}
345} // anonymous namespace
346namespace {
347at::Tensor wrapper_MkldnnCPU__tanh(const at::Tensor & self) {
348 // No device check
349 // DeviceGuard omitted
350 return at::native::mkldnn_tanh(self);
351}
352} // anonymous namespace
353namespace {
354at::Tensor & wrapper_MkldnnCPU__tanh_(at::Tensor & self) {
355 // No device check
356 // DeviceGuard omitted
357 return at::native::mkldnn_tanh_(self);
358}
359} // anonymous namespace
360namespace {
361at::Tensor wrapper_MkldnnCPU__threshold_backward(const at::Tensor & grad_output, const at::Tensor & self, const at::Scalar & threshold) {
362 // No device check
363 // DeviceGuard omitted
364 return at::native::mkldnn_relu_backward(grad_output, self, threshold);
365}
366} // anonymous namespace
367namespace {
368at::Tensor wrapper_MkldnnCPU___mkldnn_transpose(const at::Tensor & self, int64_t dim0, int64_t dim1) {
369 // No device check
370 // DeviceGuard omitted
371 return at::native::mkldnn_transpose(self, dim0, dim1);
372}
373} // anonymous namespace
374namespace {
375at::Tensor & wrapper_MkldnnCPU___mkldnn_transpose_(at::Tensor & self, int64_t dim0, int64_t dim1) {
376 // No device check
377 // DeviceGuard omitted
378 return at::native::mkldnn_transpose_(self, dim0, dim1);
379}
380} // anonymous namespace
381namespace {
382at::Tensor wrapper_MkldnnCPU__clone(const at::Tensor & self, c10::optional<at::MemoryFormat> memory_format) {
383 // No device check
384 // DeviceGuard omitted
385 return at::native::mkldnn_clone(self, memory_format);
386}
387} // anonymous namespace
388namespace {
389at::Tensor & wrapper_MkldnnCPU__zero_(at::Tensor & self) {
390 // No device check
391 // DeviceGuard omitted
392 return at::native::mkldnn_zero_(self);
393}
394} // anonymous namespace
395namespace {
396at::Tensor wrapper_MkldnnCPU___to_dense(const at::Tensor & self, c10::optional<at::ScalarType> dtype) {
397 // No device check
398 // DeviceGuard omitted
399 return at::native::mkldnn_to_dense(self, dtype);
400}
401} // anonymous namespace
402namespace {
403at::Tensor wrapper_MkldnnCPU__mkldnn_reorder_conv2d_weight(const at::Tensor & self, at::IntArrayRef padding, at::IntArrayRef stride, at::IntArrayRef dilation, int64_t groups, at::OptionalIntArrayRef input_size) {
404 // No device check
405 // DeviceGuard omitted
406 return at::native::mkldnn_reorder_conv2d_weight(self, padding, stride, dilation, groups, input_size);
407}
408} // anonymous namespace
409namespace {
410at::Tensor wrapper_MkldnnCPU__mkldnn_reorder_conv3d_weight(const at::Tensor & self, at::IntArrayRef padding, at::IntArrayRef stride, at::IntArrayRef dilation, int64_t groups) {
411 // No device check
412 // DeviceGuard omitted
413 return at::native::mkldnn_reorder_conv3d_weight(self, padding, stride, dilation, groups);
414}
415} // anonymous namespace
416namespace {
417at::Tensor wrapper_MkldnnCPU__view(const at::Tensor & self, c10::SymIntArrayRef size) {
418 // No device check
419 // DeviceGuard omitted
420 return at::native::mkldnn_view(self, C10_AS_INTARRAYREF_SLOW(size));
421}
422} // anonymous namespace
423namespace {
424at::Tensor & wrapper_MkldnnCPU_out_adaptive_avg_pool2d_out(const at::Tensor & self, c10::SymIntArrayRef output_size, at::Tensor & out) {
425 // No device check
426 // DeviceGuard omitted
427 return at::native::mkldnn_adaptive_avg_pool2d_out_stub(self, C10_AS_INTARRAYREF_SLOW(output_size), out);
428}
429} // anonymous namespace
430namespace {
431at::Tensor wrapper_MkldnnCPU__mkldnn_adaptive_avg_pool2d(const at::Tensor & self, at::IntArrayRef output_size) {
432 // No device check
433 // DeviceGuard omitted
434 return at::native::mkldnn_adaptive_avg_pool2d(self, output_size);
435}
436} // anonymous namespace
437namespace {
438at::Tensor & wrapper_MkldnnCPU_out_mkldnn_adaptive_avg_pool2d_out(const at::Tensor & self, at::IntArrayRef output_size, at::Tensor & out) {
439 // No device check
440 // DeviceGuard omitted
441 return at::native::mkldnn_adaptive_avg_pool2d_out(self, output_size, out);
442}
443} // anonymous namespace
444namespace {
445at::Tensor wrapper_MkldnnCPU__mkldnn_adaptive_avg_pool2d_backward(const at::Tensor & grad_output, const at::Tensor & self) {
446 // No device check
447 // DeviceGuard omitted
448 return at::native::mkldnn_adaptive_avg_pool2d_backward(grad_output, self);
449}
450} // anonymous namespace
451namespace {
452at::Tensor wrapper_MkldnnCPU__avg_pool2d(const at::Tensor & self, at::IntArrayRef kernel_size, at::IntArrayRef stride, at::IntArrayRef padding, bool ceil_mode, bool count_include_pad, c10::optional<int64_t> divisor_override) {
453 // No device check
454 // DeviceGuard omitted
455 return at::native::mkldnn_avg_pool2d(self, kernel_size, stride, padding, ceil_mode, count_include_pad, divisor_override);
456}
457} // anonymous namespace
458namespace {
459at::Tensor & wrapper_MkldnnCPU_out_avg_pool2d_out(const at::Tensor & self, at::IntArrayRef kernel_size, at::IntArrayRef stride, at::IntArrayRef padding, bool ceil_mode, bool count_include_pad, c10::optional<int64_t> divisor_override, at::Tensor & out) {
460 // No device check
461 // DeviceGuard omitted
462 return at::native::mkldnn_avg_pool2d_out(self, kernel_size, stride, padding, ceil_mode, count_include_pad, divisor_override, out);
463}
464} // anonymous namespace
465namespace {
466at::Tensor wrapper_MkldnnCPU__avg_pool2d_backward(const at::Tensor & grad_output, const at::Tensor & self, at::IntArrayRef kernel_size, at::IntArrayRef stride, at::IntArrayRef padding, bool ceil_mode, bool count_include_pad, c10::optional<int64_t> divisor_override) {
467 // No device check
468 // DeviceGuard omitted
469 return at::native::mkldnn_avg_pool2d_backward(grad_output, self, kernel_size, stride, padding, ceil_mode, count_include_pad, divisor_override);
470}
471} // anonymous namespace
472namespace {
473at::Tensor & wrapper_MkldnnCPU_grad_input_avg_pool2d_backward_out(const at::Tensor & grad_output, const at::Tensor & self, at::IntArrayRef kernel_size, at::IntArrayRef stride, at::IntArrayRef padding, bool ceil_mode, bool count_include_pad, c10::optional<int64_t> divisor_override, at::Tensor & grad_input) {
474 // No device check
475 // DeviceGuard omitted
476 return at::native::mkldnn_avg_pool2d_backward_out(grad_output, self, kernel_size, stride, padding, ceil_mode, count_include_pad, divisor_override, grad_input);
477}
478} // anonymous namespace
479namespace {
480at::Tensor wrapper_MkldnnCPU__avg_pool3d(const at::Tensor & self, at::IntArrayRef kernel_size, at::IntArrayRef stride, at::IntArrayRef padding, bool ceil_mode, bool count_include_pad, c10::optional<int64_t> divisor_override) {
481 // No device check
482 // DeviceGuard omitted
483 return at::native::mkldnn_avg_pool3d(self, kernel_size, stride, padding, ceil_mode, count_include_pad, divisor_override);
484}
485} // anonymous namespace
486namespace {
487at::Tensor & wrapper_MkldnnCPU_out_avg_pool3d_out(const at::Tensor & self, at::IntArrayRef kernel_size, at::IntArrayRef stride, at::IntArrayRef padding, bool ceil_mode, bool count_include_pad, c10::optional<int64_t> divisor_override, at::Tensor & out) {
488 // No device check
489 // DeviceGuard omitted
490 return at::native::mkldnn_avg_pool3d_out(self, kernel_size, stride, padding, ceil_mode, count_include_pad, divisor_override, out);
491}
492} // anonymous namespace
493namespace {
494at::Tensor wrapper_MkldnnCPU__avg_pool3d_backward(const at::Tensor & grad_output, const at::Tensor & self, at::IntArrayRef kernel_size, at::IntArrayRef stride, at::IntArrayRef padding, bool ceil_mode, bool count_include_pad, c10::optional<int64_t> divisor_override) {
495 // No device check
496 // DeviceGuard omitted
497 return at::native::mkldnn_avg_pool3d_backward(grad_output, self, kernel_size, stride, padding, ceil_mode, count_include_pad, divisor_override);
498}
499} // anonymous namespace
500namespace {
501at::Tensor & wrapper_MkldnnCPU_grad_input_avg_pool3d_backward_out(const at::Tensor & grad_output, const at::Tensor & self, at::IntArrayRef kernel_size, at::IntArrayRef stride, at::IntArrayRef padding, bool ceil_mode, bool count_include_pad, c10::optional<int64_t> divisor_override, at::Tensor & grad_input) {
502 // No device check
503 // DeviceGuard omitted
504 return at::native::mkldnn_avg_pool3d_backward_out(grad_output, self, kernel_size, stride, padding, ceil_mode, count_include_pad, divisor_override, grad_input);
505}
506} // anonymous namespace
507TORCH_LIBRARY_IMPL(aten, MkldnnCPU, m) {
508 m.impl("add.Tensor",
509TORCH_FN(wrapper_MkldnnCPU_Tensor_add));
510m.impl("add.out",
511TORCH_FN(wrapper_MkldnnCPU_out_add_out));
512m.impl("add_.Tensor",
513TORCH_FN(wrapper_MkldnnCPU_Tensor_add_));
514m.impl("copy_",
515TORCH_FN(wrapper_MkldnnCPU__copy_));
516m.impl("empty.memory_format",
517TORCH_FN(wrapper_MkldnnCPU_memory_format_empty));
518m.impl("mkldnn_linear",
519TORCH_FN(wrapper_MkldnnCPU__mkldnn_linear));
520m.impl("mkldnn_linear_backward_input",
521TORCH_FN(wrapper_MkldnnCPU__mkldnn_linear_backward_input));
522m.impl("mkldnn_linear_backward_weights",
523TORCH_FN(wrapper_MkldnnCPU__mkldnn_linear_backward_weights));
524m.impl("mkldnn_linear_backward",
525TORCH_FN(wrapper_MkldnnCPU__mkldnn_linear_backward));
526m.impl("mkldnn_max_pool2d",
527TORCH_FN(wrapper_MkldnnCPU__mkldnn_max_pool2d));
528m.impl("mkldnn_max_pool2d_backward",
529TORCH_FN(wrapper_MkldnnCPU__mkldnn_max_pool2d_backward));
530m.impl("mkldnn_max_pool3d",
531TORCH_FN(wrapper_MkldnnCPU__mkldnn_max_pool3d));
532m.impl("mkldnn_max_pool3d_backward",
533TORCH_FN(wrapper_MkldnnCPU__mkldnn_max_pool3d_backward));
534m.impl("mul.Tensor",
535TORCH_FN(wrapper_MkldnnCPU_Tensor_mul));
536m.impl("mul.out",
537TORCH_FN(wrapper_MkldnnCPU_out_mul_out));
538m.impl("mul_.Tensor",
539TORCH_FN(wrapper_MkldnnCPU_Tensor_mul_));
540m.impl("native_batch_norm",
541TORCH_FN(wrapper_MkldnnCPU__native_batch_norm));
542m.impl("_native_batch_norm_legit",
543TORCH_FN(wrapper_MkldnnCPU___native_batch_norm_legit));
544m.impl("_native_batch_norm_legit.no_stats",
545TORCH_FN(wrapper_MkldnnCPU_no_stats__native_batch_norm_legit));
546m.impl("native_batch_norm_backward",
547TORCH_FN(wrapper_MkldnnCPU__native_batch_norm_backward));
548m.impl("_mkldnn_reshape",
549TORCH_FN(wrapper_MkldnnCPU___mkldnn_reshape));
550m.impl("relu",
551TORCH_FN(wrapper_MkldnnCPU__relu));
552m.impl("relu_",
553TORCH_FN(wrapper_MkldnnCPU__relu_));
554m.impl("_prelu_kernel",
555TORCH_FN(wrapper_MkldnnCPU___prelu_kernel));
556m.impl("_prelu_kernel_backward",
557TORCH_FN(wrapper_MkldnnCPU___prelu_kernel_backward));
558m.impl("gelu",
559TORCH_FN(wrapper_MkldnnCPU__gelu));
560m.impl("gelu_backward",
561TORCH_FN(wrapper_MkldnnCPU__gelu_backward));
562m.impl("sigmoid",
563TORCH_FN(wrapper_MkldnnCPU__sigmoid));
564m.impl("sigmoid_",
565TORCH_FN(wrapper_MkldnnCPU__sigmoid_));
566m.impl("_softmax",
567TORCH_FN(wrapper_MkldnnCPU___softmax));
568m.impl("tanh",
569TORCH_FN(wrapper_MkldnnCPU__tanh));
570m.impl("tanh_",
571TORCH_FN(wrapper_MkldnnCPU__tanh_));
572m.impl("threshold_backward",
573TORCH_FN(wrapper_MkldnnCPU__threshold_backward));
574m.impl("_mkldnn_transpose",
575TORCH_FN(wrapper_MkldnnCPU___mkldnn_transpose));
576m.impl("_mkldnn_transpose_",
577TORCH_FN(wrapper_MkldnnCPU___mkldnn_transpose_));
578m.impl("clone",
579TORCH_FN(wrapper_MkldnnCPU__clone));
580m.impl("zero_",
581TORCH_FN(wrapper_MkldnnCPU__zero_));
582m.impl("_to_dense",
583TORCH_FN(wrapper_MkldnnCPU___to_dense));
584m.impl("mkldnn_reorder_conv2d_weight",
585TORCH_FN(wrapper_MkldnnCPU__mkldnn_reorder_conv2d_weight));
586m.impl("mkldnn_reorder_conv3d_weight",
587TORCH_FN(wrapper_MkldnnCPU__mkldnn_reorder_conv3d_weight));
588m.impl("view",
589TORCH_FN(wrapper_MkldnnCPU__view));
590m.impl("adaptive_avg_pool2d.out",
591TORCH_FN(wrapper_MkldnnCPU_out_adaptive_avg_pool2d_out));
592m.impl("mkldnn_adaptive_avg_pool2d",
593TORCH_FN(wrapper_MkldnnCPU__mkldnn_adaptive_avg_pool2d));
594m.impl("mkldnn_adaptive_avg_pool2d.out",
595TORCH_FN(wrapper_MkldnnCPU_out_mkldnn_adaptive_avg_pool2d_out));
596m.impl("mkldnn_adaptive_avg_pool2d_backward",
597TORCH_FN(wrapper_MkldnnCPU__mkldnn_adaptive_avg_pool2d_backward));
598m.impl("avg_pool2d",
599TORCH_FN(wrapper_MkldnnCPU__avg_pool2d));
600m.impl("avg_pool2d.out",
601TORCH_FN(wrapper_MkldnnCPU_out_avg_pool2d_out));
602m.impl("avg_pool2d_backward",
603TORCH_FN(wrapper_MkldnnCPU__avg_pool2d_backward));
604m.impl("avg_pool2d_backward.grad_input",
605TORCH_FN(wrapper_MkldnnCPU_grad_input_avg_pool2d_backward_out));
606m.impl("avg_pool3d",
607TORCH_FN(wrapper_MkldnnCPU__avg_pool3d));
608m.impl("avg_pool3d.out",
609TORCH_FN(wrapper_MkldnnCPU_out_avg_pool3d_out));
610m.impl("avg_pool3d_backward",
611TORCH_FN(wrapper_MkldnnCPU__avg_pool3d_backward));
612m.impl("avg_pool3d_backward.grad_input",
613TORCH_FN(wrapper_MkldnnCPU_grad_input_avg_pool3d_backward_out));
614};
615} // anonymous namespace
616namespace mkldnncpu {
617at::Tensor add(const at::Tensor & self, const at::Tensor & other, const at::Scalar & alpha) {
618return wrapper_MkldnnCPU_Tensor_add(self, other, alpha);
619}
620at::Tensor & add_out(at::Tensor & out, const at::Tensor & self, const at::Tensor & other, const at::Scalar & alpha) {
621return wrapper_MkldnnCPU_out_add_out(self, other, alpha, out);
622}
623at::Tensor & add_outf(const at::Tensor & self, const at::Tensor & other, const at::Scalar & alpha, at::Tensor & out) {
624return wrapper_MkldnnCPU_out_add_out(self, other, alpha, out);
625}
626at::Tensor & add_(at::Tensor & self, const at::Tensor & other, const at::Scalar & alpha) {
627return wrapper_MkldnnCPU_Tensor_add_(self, other, alpha);
628}
629at::Tensor & copy_(at::Tensor & self, const at::Tensor & src, bool non_blocking) {
630return wrapper_MkldnnCPU__copy_(self, src, non_blocking);
631}
632at::Tensor empty(at::IntArrayRef size, at::TensorOptions options, c10::optional<at::MemoryFormat> memory_format) {
633return wrapper_MkldnnCPU_memory_format_empty(c10::fromIntArrayRefSlow(size), optTypeMetaToScalarType(options.dtype_opt()), options.layout_opt(), options.device_opt(), options.pinned_memory_opt(), c10::impl::check_tensor_options_and_extract_memory_format(options, memory_format));
634}
635at::Tensor empty(at::IntArrayRef size, c10::optional<at::ScalarType> dtype, c10::optional<at::Layout> layout, c10::optional<at::Device> device, c10::optional<bool> pin_memory, c10::optional<at::MemoryFormat> memory_format) {
636return wrapper_MkldnnCPU_memory_format_empty(c10::fromIntArrayRefSlow(size), dtype, layout, device, pin_memory, memory_format);
637}
638at::Tensor empty_symint(c10::SymIntArrayRef size, at::TensorOptions options, c10::optional<at::MemoryFormat> memory_format) {
639return wrapper_MkldnnCPU_memory_format_empty(size, optTypeMetaToScalarType(options.dtype_opt()), options.layout_opt(), options.device_opt(), options.pinned_memory_opt(), c10::impl::check_tensor_options_and_extract_memory_format(options, memory_format));
640}
641at::Tensor empty_symint(c10::SymIntArrayRef size, c10::optional<at::ScalarType> dtype, c10::optional<at::Layout> layout, c10::optional<at::Device> device, c10::optional<bool> pin_memory, c10::optional<at::MemoryFormat> memory_format) {
642return wrapper_MkldnnCPU_memory_format_empty(size, dtype, layout, device, pin_memory, memory_format);
643}
644at::Tensor mkldnn_linear(const at::Tensor & self, const at::Tensor & weight, const c10::optional<at::Tensor> & bias) {
645return wrapper_MkldnnCPU__mkldnn_linear(self, weight, bias);
646}
647at::Tensor mkldnn_linear_backward_input(at::IntArrayRef input_size, const at::Tensor & grad_output, const at::Tensor & weight) {
648return wrapper_MkldnnCPU__mkldnn_linear_backward_input(input_size, grad_output, weight);
649}
650::std::tuple<at::Tensor,at::Tensor> mkldnn_linear_backward_weights(const at::Tensor & grad_output, const at::Tensor & input, const at::Tensor & weight, bool bias_defined) {
651return wrapper_MkldnnCPU__mkldnn_linear_backward_weights(grad_output, input, weight, bias_defined);
652}
653::std::tuple<at::Tensor,at::Tensor,at::Tensor> mkldnn_linear_backward(const at::Tensor & self, const at::Tensor & grad_output, const at::Tensor & weight, ::std::array<bool,3> output_mask) {
654return wrapper_MkldnnCPU__mkldnn_linear_backward(self, grad_output, weight, output_mask);
655}
656at::Tensor mkldnn_max_pool2d(const at::Tensor & self, at::IntArrayRef kernel_size, at::IntArrayRef stride, at::IntArrayRef padding, at::IntArrayRef dilation, bool ceil_mode) {
657return wrapper_MkldnnCPU__mkldnn_max_pool2d(self, kernel_size, stride, padding, dilation, ceil_mode);
658}
659at::Tensor mkldnn_max_pool2d_backward(const at::Tensor & grad_output, const at::Tensor & output, const at::Tensor & input, at::IntArrayRef kernel_size, at::IntArrayRef stride, at::IntArrayRef padding, at::IntArrayRef dilation, bool ceil_mode) {
660return wrapper_MkldnnCPU__mkldnn_max_pool2d_backward(grad_output, output, input, kernel_size, stride, padding, dilation, ceil_mode);
661}
662at::Tensor mkldnn_max_pool3d(const at::Tensor & self, at::IntArrayRef kernel_size, at::IntArrayRef stride, at::IntArrayRef padding, at::IntArrayRef dilation, bool ceil_mode) {
663return wrapper_MkldnnCPU__mkldnn_max_pool3d(self, kernel_size, stride, padding, dilation, ceil_mode);
664}
665at::Tensor mkldnn_max_pool3d_backward(const at::Tensor & grad_output, const at::Tensor & output, const at::Tensor & input, at::IntArrayRef kernel_size, at::IntArrayRef stride, at::IntArrayRef padding, at::IntArrayRef dilation, bool ceil_mode) {
666return wrapper_MkldnnCPU__mkldnn_max_pool3d_backward(grad_output, output, input, kernel_size, stride, padding, dilation, ceil_mode);
667}
668at::Tensor mul(const at::Tensor & self, const at::Tensor & other) {
669return wrapper_MkldnnCPU_Tensor_mul(self, other);
670}
671at::Tensor & mul_out(at::Tensor & out, const at::Tensor & self, const at::Tensor & other) {
672return wrapper_MkldnnCPU_out_mul_out(self, other, out);
673}
674at::Tensor & mul_outf(const at::Tensor & self, const at::Tensor & other, at::Tensor & out) {
675return wrapper_MkldnnCPU_out_mul_out(self, other, out);
676}
677at::Tensor & mul_(at::Tensor & self, const at::Tensor & other) {
678return wrapper_MkldnnCPU_Tensor_mul_(self, other);
679}
680::std::tuple<at::Tensor,at::Tensor,at::Tensor> native_batch_norm(const at::Tensor & input, const c10::optional<at::Tensor> & weight, const c10::optional<at::Tensor> & bias, const c10::optional<at::Tensor> & running_mean, const c10::optional<at::Tensor> & running_var, bool training, double momentum, double eps) {
681return wrapper_MkldnnCPU__native_batch_norm(input, weight, bias, running_mean, running_var, training, momentum, eps);
682}
683::std::tuple<at::Tensor,at::Tensor,at::Tensor> _native_batch_norm_legit(const at::Tensor & input, const c10::optional<at::Tensor> & weight, const c10::optional<at::Tensor> & bias, at::Tensor & running_mean, at::Tensor & running_var, bool training, double momentum, double eps) {
684return wrapper_MkldnnCPU___native_batch_norm_legit(input, weight, bias, running_mean, running_var, training, momentum, eps);
685}
686::std::tuple<at::Tensor,at::Tensor,at::Tensor> _native_batch_norm_legit(const at::Tensor & input, const c10::optional<at::Tensor> & weight, const c10::optional<at::Tensor> & bias, bool training, double momentum, double eps) {
687return wrapper_MkldnnCPU_no_stats__native_batch_norm_legit(input, weight, bias, training, momentum, eps);
688}
689::std::tuple<at::Tensor,at::Tensor,at::Tensor> native_batch_norm_backward(const at::Tensor & grad_out, const at::Tensor & input, const c10::optional<at::Tensor> & weight, const c10::optional<at::Tensor> & running_mean, const c10::optional<at::Tensor> & running_var, const c10::optional<at::Tensor> & save_mean, const c10::optional<at::Tensor> & save_invstd, bool train, double eps, ::std::array<bool,3> output_mask) {
690return wrapper_MkldnnCPU__native_batch_norm_backward(grad_out, input, weight, running_mean, running_var, save_mean, save_invstd, train, eps, output_mask);
691}
692at::Tensor _mkldnn_reshape(const at::Tensor & self, at::IntArrayRef shape) {
693return wrapper_MkldnnCPU___mkldnn_reshape(self, shape);
694}
695at::Tensor relu(const at::Tensor & self) {
696return wrapper_MkldnnCPU__relu(self);
697}
698at::Tensor & relu_(at::Tensor & self) {
699return wrapper_MkldnnCPU__relu_(self);
700}
701at::Tensor _prelu_kernel(const at::Tensor & self, const at::Tensor & weight) {
702return wrapper_MkldnnCPU___prelu_kernel(self, weight);
703}
704::std::tuple<at::Tensor,at::Tensor> _prelu_kernel_backward(const at::Tensor & grad_output, const at::Tensor & self, const at::Tensor & weight) {
705return wrapper_MkldnnCPU___prelu_kernel_backward(grad_output, self, weight);
706}
707at::Tensor gelu(const at::Tensor & self, c10::string_view approximate) {
708return wrapper_MkldnnCPU__gelu(self, approximate);
709}
710at::Tensor gelu_backward(const at::Tensor & grad_output, const at::Tensor & self, c10::string_view approximate) {
711return wrapper_MkldnnCPU__gelu_backward(grad_output, self, approximate);
712}
713at::Tensor sigmoid(const at::Tensor & self) {
714return wrapper_MkldnnCPU__sigmoid(self);
715}
716at::Tensor & sigmoid_(at::Tensor & self) {
717return wrapper_MkldnnCPU__sigmoid_(self);
718}
719at::Tensor _softmax(const at::Tensor & self, int64_t dim, bool half_to_float) {
720return wrapper_MkldnnCPU___softmax(self, dim, half_to_float);
721}
722at::Tensor tanh(const at::Tensor & self) {
723return wrapper_MkldnnCPU__tanh(self);
724}
725at::Tensor & tanh_(at::Tensor & self) {
726return wrapper_MkldnnCPU__tanh_(self);
727}
728at::Tensor threshold_backward(const at::Tensor & grad_output, const at::Tensor & self, const at::Scalar & threshold) {
729return wrapper_MkldnnCPU__threshold_backward(grad_output, self, threshold);
730}
731at::Tensor _mkldnn_transpose(const at::Tensor & self, int64_t dim0, int64_t dim1) {
732return wrapper_MkldnnCPU___mkldnn_transpose(self, dim0, dim1);
733}
734at::Tensor & _mkldnn_transpose_(at::Tensor & self, int64_t dim0, int64_t dim1) {
735return wrapper_MkldnnCPU___mkldnn_transpose_(self, dim0, dim1);
736}
737at::Tensor clone(const at::Tensor & self, c10::optional<at::MemoryFormat> memory_format) {
738return wrapper_MkldnnCPU__clone(self, memory_format);
739}
740at::Tensor & zero_(at::Tensor & self) {
741return wrapper_MkldnnCPU__zero_(self);
742}
743at::Tensor _to_dense(const at::Tensor & self, c10::optional<at::ScalarType> dtype) {
744return wrapper_MkldnnCPU___to_dense(self, dtype);
745}
746at::Tensor mkldnn_reorder_conv2d_weight(const at::Tensor & self, at::IntArrayRef padding, at::IntArrayRef stride, at::IntArrayRef dilation, int64_t groups, at::OptionalIntArrayRef input_size) {
747return wrapper_MkldnnCPU__mkldnn_reorder_conv2d_weight(self, padding, stride, dilation, groups, input_size);
748}
749at::Tensor mkldnn_reorder_conv3d_weight(const at::Tensor & self, at::IntArrayRef padding, at::IntArrayRef stride, at::IntArrayRef dilation, int64_t groups) {
750return wrapper_MkldnnCPU__mkldnn_reorder_conv3d_weight(self, padding, stride, dilation, groups);
751}
752at::Tensor view(const at::Tensor & self, at::IntArrayRef size) {
753return wrapper_MkldnnCPU__view(self, c10::fromIntArrayRefSlow(size));
754}
755at::Tensor view_symint(const at::Tensor & self, c10::SymIntArrayRef size) {
756return wrapper_MkldnnCPU__view(self, size);
757}
758at::Tensor & adaptive_avg_pool2d_out(at::Tensor & out, const at::Tensor & self, at::IntArrayRef output_size) {
759return wrapper_MkldnnCPU_out_adaptive_avg_pool2d_out(self, c10::fromIntArrayRefSlow(output_size), out);
760}
761at::Tensor & adaptive_avg_pool2d_outf(const at::Tensor & self, at::IntArrayRef output_size, at::Tensor & out) {
762return wrapper_MkldnnCPU_out_adaptive_avg_pool2d_out(self, c10::fromIntArrayRefSlow(output_size), out);
763}
764at::Tensor & adaptive_avg_pool2d_symint_out(at::Tensor & out, const at::Tensor & self, c10::SymIntArrayRef output_size) {
765return wrapper_MkldnnCPU_out_adaptive_avg_pool2d_out(self, output_size, out);
766}
767at::Tensor & adaptive_avg_pool2d_symint_outf(const at::Tensor & self, c10::SymIntArrayRef output_size, at::Tensor & out) {
768return wrapper_MkldnnCPU_out_adaptive_avg_pool2d_out(self, output_size, out);
769}
770at::Tensor mkldnn_adaptive_avg_pool2d(const at::Tensor & self, at::IntArrayRef output_size) {
771return wrapper_MkldnnCPU__mkldnn_adaptive_avg_pool2d(self, output_size);
772}
773at::Tensor & mkldnn_adaptive_avg_pool2d_out(at::Tensor & out, const at::Tensor & self, at::IntArrayRef output_size) {
774return wrapper_MkldnnCPU_out_mkldnn_adaptive_avg_pool2d_out(self, output_size, out);
775}
776at::Tensor & mkldnn_adaptive_avg_pool2d_outf(const at::Tensor & self, at::IntArrayRef output_size, at::Tensor & out) {
777return wrapper_MkldnnCPU_out_mkldnn_adaptive_avg_pool2d_out(self, output_size, out);
778}
779at::Tensor mkldnn_adaptive_avg_pool2d_backward(const at::Tensor & grad_output, const at::Tensor & self) {
780return wrapper_MkldnnCPU__mkldnn_adaptive_avg_pool2d_backward(grad_output, self);
781}
782at::Tensor avg_pool2d(const at::Tensor & self, at::IntArrayRef kernel_size, at::IntArrayRef stride, at::IntArrayRef padding, bool ceil_mode, bool count_include_pad, c10::optional<int64_t> divisor_override) {
783return wrapper_MkldnnCPU__avg_pool2d(self, kernel_size, stride, padding, ceil_mode, count_include_pad, divisor_override);
784}
785at::Tensor & avg_pool2d_out(at::Tensor & out, const at::Tensor & self, at::IntArrayRef kernel_size, at::IntArrayRef stride, at::IntArrayRef padding, bool ceil_mode, bool count_include_pad, c10::optional<int64_t> divisor_override) {
786return wrapper_MkldnnCPU_out_avg_pool2d_out(self, kernel_size, stride, padding, ceil_mode, count_include_pad, divisor_override, out);
787}
788at::Tensor & avg_pool2d_outf(const at::Tensor & self, at::IntArrayRef kernel_size, at::IntArrayRef stride, at::IntArrayRef padding, bool ceil_mode, bool count_include_pad, c10::optional<int64_t> divisor_override, at::Tensor & out) {
789return wrapper_MkldnnCPU_out_avg_pool2d_out(self, kernel_size, stride, padding, ceil_mode, count_include_pad, divisor_override, out);
790}
791at::Tensor avg_pool2d_backward(const at::Tensor & grad_output, const at::Tensor & self, at::IntArrayRef kernel_size, at::IntArrayRef stride, at::IntArrayRef padding, bool ceil_mode, bool count_include_pad, c10::optional<int64_t> divisor_override) {
792return wrapper_MkldnnCPU__avg_pool2d_backward(grad_output, self, kernel_size, stride, padding, ceil_mode, count_include_pad, divisor_override);
793}
794at::Tensor & avg_pool2d_backward_out(at::Tensor & grad_input, const at::Tensor & grad_output, const at::Tensor & self, at::IntArrayRef kernel_size, at::IntArrayRef stride, at::IntArrayRef padding, bool ceil_mode, bool count_include_pad, c10::optional<int64_t> divisor_override) {
795return wrapper_MkldnnCPU_grad_input_avg_pool2d_backward_out(grad_output, self, kernel_size, stride, padding, ceil_mode, count_include_pad, divisor_override, grad_input);
796}
797at::Tensor & avg_pool2d_backward_outf(const at::Tensor & grad_output, const at::Tensor & self, at::IntArrayRef kernel_size, at::IntArrayRef stride, at::IntArrayRef padding, bool ceil_mode, bool count_include_pad, c10::optional<int64_t> divisor_override, at::Tensor & grad_input) {
798return wrapper_MkldnnCPU_grad_input_avg_pool2d_backward_out(grad_output, self, kernel_size, stride, padding, ceil_mode, count_include_pad, divisor_override, grad_input);
799}
800at::Tensor avg_pool3d(const at::Tensor & self, at::IntArrayRef kernel_size, at::IntArrayRef stride, at::IntArrayRef padding, bool ceil_mode, bool count_include_pad, c10::optional<int64_t> divisor_override) {
801return wrapper_MkldnnCPU__avg_pool3d(self, kernel_size, stride, padding, ceil_mode, count_include_pad, divisor_override);
802}
803at::Tensor & avg_pool3d_out(at::Tensor & out, const at::Tensor & self, at::IntArrayRef kernel_size, at::IntArrayRef stride, at::IntArrayRef padding, bool ceil_mode, bool count_include_pad, c10::optional<int64_t> divisor_override) {
804return wrapper_MkldnnCPU_out_avg_pool3d_out(self, kernel_size, stride, padding, ceil_mode, count_include_pad, divisor_override, out);
805}
806at::Tensor & avg_pool3d_outf(const at::Tensor & self, at::IntArrayRef kernel_size, at::IntArrayRef stride, at::IntArrayRef padding, bool ceil_mode, bool count_include_pad, c10::optional<int64_t> divisor_override, at::Tensor & out) {
807return wrapper_MkldnnCPU_out_avg_pool3d_out(self, kernel_size, stride, padding, ceil_mode, count_include_pad, divisor_override, out);
808}
809at::Tensor avg_pool3d_backward(const at::Tensor & grad_output, const at::Tensor & self, at::IntArrayRef kernel_size, at::IntArrayRef stride, at::IntArrayRef padding, bool ceil_mode, bool count_include_pad, c10::optional<int64_t> divisor_override) {
810return wrapper_MkldnnCPU__avg_pool3d_backward(grad_output, self, kernel_size, stride, padding, ceil_mode, count_include_pad, divisor_override);
811}
812at::Tensor & avg_pool3d_backward_out(at::Tensor & grad_input, const at::Tensor & grad_output, const at::Tensor & self, at::IntArrayRef kernel_size, at::IntArrayRef stride, at::IntArrayRef padding, bool ceil_mode, bool count_include_pad, c10::optional<int64_t> divisor_override) {
813return wrapper_MkldnnCPU_grad_input_avg_pool3d_backward_out(grad_output, self, kernel_size, stride, padding, ceil_mode, count_include_pad, divisor_override, grad_input);
814}
815at::Tensor & avg_pool3d_backward_outf(const at::Tensor & grad_output, const at::Tensor & self, at::IntArrayRef kernel_size, at::IntArrayRef stride, at::IntArrayRef padding, bool ceil_mode, bool count_include_pad, c10::optional<int64_t> divisor_override, at::Tensor & grad_input) {
816return wrapper_MkldnnCPU_grad_input_avg_pool3d_backward_out(grad_output, self, kernel_size, stride, padding, ceil_mode, count_include_pad, divisor_override, grad_input);
817}
818} // namespace mkldnncpu
819} // namespace at
820