1namespace dnnl {
2namespace impl {
3namespace gpu {
4namespace ocl {
5const char *zero_pad_struct_header = R"==(/******************************************************************************* )==""\n"
6R"==(* Copyright 2020-2021 Intel Corporation )==""\n"
7R"==(* )==""\n"
8R"==(* Licensed under the Apache License, Version 2.0 (the "License"); )==""\n"
9R"==(* you may not use this file except in compliance with the License. )==""\n"
10R"==(* You may obtain a copy of the License at )==""\n"
11R"==(* )==""\n"
12R"==(* http: )==""\n"
13R"==(* )==""\n"
14R"==(* Unless required by applicable law or agreed to in writing, software )==""\n"
15R"==(* distributed under the License is distributed on an "AS IS" BASIS, )==""\n"
16R"==(* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. )==""\n"
17R"==(* See the License for the specific language governing permissions and )==""\n"
18R"==(* limitations under the License. )==""\n"
19R"==(*******************************************************************************/ )==""\n"
20R"==(#ifndef GPU_ZERO_PAD_ZERO_PAD_STRUCT_H )==""\n"
21R"==(#define GPU_ZERO_PAD_ZERO_PAD_STRUCT_H )==""\n"
22R"==(#define ZERO_PAD_MAX_STEP_SIZE 1536 )==""\n"
23R"==(#ifdef IS_OCL_KERNEL )==""\n"
24R"==(#define ZERO_PAD_MASK_DATA_TYPE uchar )==""\n"
25R"==(#else )==""\n"
26R"==(#define ZERO_PAD_MASK_DATA_TYPE unsigned char )==""\n"
27R"==(#endif )==""\n"
28R"==(#define ZERO_PAD_MASK_DT_BITS (8 * sizeof(ZERO_PAD_MASK_DATA_TYPE)) )==""\n"
29R"==(#define ZERO_PAD_MASK_SIZE (ZERO_PAD_MAX_STEP_SIZE / ZERO_PAD_MASK_DT_BITS) )==""\n"
30R"==(#define ZERO_PAD_BIT_MODE 0 )==""\n"
31R"==(#define ZERO_PAD_LOOKUP_MODE 1 )==""\n"
32R"==(typedef struct { )==""\n"
33R"==(ZERO_PAD_MASK_DATA_TYPE mask[ZERO_PAD_MASK_SIZE]; )==""\n"
34R"==(} zero_pad_mask_t; )==""\n"
35R"==(#endif )==""\n"
36R"==()==";
37}
38}
39}
40}